# High Throughput Sine and Cosine (Clock-Driven Logic)

Last Modified: February 27, 2020

Computes both the sine and cosine of a specified value (x). You must specify x in pi radians, which use fewer FPGA resources than radians. To convert a radian value to pi radians, multiply the value by pi.

## x

An input to this operation.

You must specify this input in pi radians, which use fewer resources than radians. To convert radians to pi radians, multiply the radian value by pi.

## input valid

Boolean value that describes whether the next data element has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

 True The next data element has arrived for processing. False The next data element has not arrived for processing.

## ready for output

Boolean value that specifies whether downstream nodes are ready for this node to return a new value.

Use Feedback Node to wire this input to the ready for input input of a downstream node. If this input is False during a given cycle, output valid returns False during that cycle.

 True The downstream node is ready for the next data element. False The downstream node is not ready for the next data element.

Default: False

## sin(x)

Result of the operation in pi radians, which uses fewer resources on the FPGA.

This output assumes the same numeric representation as x. When x is of the form x = a + bi, that is, when x is complex, the following equation defines sin:
$\mathrm{sin}\left(x\right)=\mathrm{sin}\left(a\right)*\mathrm{cosh}\left(b\right)+i\left(\mathrm{cos}\left(a\right)*\mathrm{sinh}\left(b\right)\right)$

## cos(x)

Result of the operation in pi radians, which uses fewer resources on the FPGA.

This output assumes the same numeric representation as x. When x is of the form x = a + bi, that is, when x is complex, the following equation defines cos:
$\mathrm{cos}\left(x\right)=\mathrm{cos}\left(a\right)*\mathrm{cosh}\left(b\right)+i\left(-\mathrm{sin}\left(a\right)*\mathrm{sinh}\left(b\right)\right)$

## output valid

Boolean value that indicates whether this node computes a result that downstream nodes can use.

Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

 True Downstream nodes can use the result this node computes. False This node returns an undefined value that downstream nodes cannot use. Note This node may return different undefined values when executed in simulation mode versus when executed on hardware.

## ready for input

Boolean value that indicates whether this node is ready to accept new input data.

Use Feedback Node to wire this output to the ready for output output of an upstream node.

 True The node is ready to accept new input data. False The node is not ready to accept new input data.
Note

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application