Table Of Contents

FFT (Single Channel, Multiple Samples) (Clock-Driven Logic)

Last Modified: February 28, 2020

Computes the fast Fourier transform (FFT) of the input signal stream with multiple samples per cycle.

This node allows you to process FPGA I/O with multiple samples per data clock cycle. This node achieves higher data throughput but consumes significantly more FPGA resources than the FFT (Single Channel, Single Sample) node.

connector_pane_image
datatype_icon

reset

Boolean value that specifies whether to reset the internal state of the node.

True Resets the internal state of the node.
False Does not reset the internal state of the node.

Behavior with Handshaking Inputs and Outputs

The handshaking inputs and outputs on this node behave as follows during the cycles where reset is True:

  • input valid is ignored.
  • ready for output is ignored.
  • output valid is False.
  • ready for input is False, which handles cases where reset is held True for more than one cycle. This node is ready for inputs after the reset is complete and reset returns False.

Default: False

datatype_icon

data in

Input stream of signals for which you want to compute the FFT.

This input accepts an array of the following data types:
  • 8-bit signed integer
  • 8-bit unsigned integer
  • 16-bit signed integer
  • 16-bit unsigned integer
  • 32-bit signed integer
  • fixed-point numeric
  • complex fixed-point numeric

The array size must be 2, 4, 8, or 16. For each array element, the maximum word length is 32 bits.

datatype_icon

input valid

Boolean value that describes whether the next data element has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

True The next data element has arrived for processing.
False The next data element has not arrived for processing.
datatype_icon

ready for output

Boolean value that defines whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

True Downstream nodes are ready for this node to return a new value.
False Downstream nodes are not ready for this node to return a new value.
spd-note-note
Note

If this input is False during a cycle, the output valid output returns False during that cycle.

Default: True

datatype_icon

data out

FFT results of the input stream of signals.

The maximum word length of each FFT result is 32 bits.

Customizing the Word Length of the FFT Results

Typically, the word length of each FFT result is log2 (N)+1 bits larger than the corresponding input data, where N is the FFT size. You can customize the word length of the FFT results by clicking the Complex fixed-point configurator button next to the Precision control in the Terminals section of the Item tab.

Decreasing the output word length conserves FPGA resources but reduces precision. NI recommends that you simulate a given configuration to ensure that the precision you achieve meets your application requirements.

datatype_icon

data index

Indexes of the FFT bins this node returns.

datatype_icon

output valid

Boolean value that indicates whether this node computes a result that downstream nodes can use.

Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

True Downstream nodes can use the result this node computes.
False This node returns an undefined value that downstream nodes cannot use.
spd-note-note
Note

This node may return different undefined values when executed in simulation mode versus when executed on hardware.

datatype_icon

ready for input

Boolean value that determines whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

True This node is ready to accept new input data.
False This node is not ready to accept new input data.
spd-note-note
Note

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if the input valid input is True during the following cycle.

Timing Diagram

The throughput for this node is 1 cycle per input, which means this node accepts new data every cycle. The following diagram demonstrates the timing this node uses.

Avoiding Data Loss During FFT Calculation

This node does not accept or return values while calculating the FFT. During this time, if the system or another node sends data to this node, this node discards the data. This might happen if this node receives data as part of a complicated or non-uniform pattern.

To avoid data loss, create a FIFO to hold data until this node accepts values again. Ensure that the FIFO you create is large enough to hold all data points that collect while the node calculates the FFT. To roughly estimate the size of the FIFO you need to create, divide the latency of this node by the average system throughput. The latency is in the Performance section of the Item tab of the configuration pane.

Understanding the Input/Output Index Pattern

In the Interface section of the Item tab of the configuration pane, you can configure this node to use the Continuous in/M-interval out or M-interval in/Continuous out index pattern.

The following table compares and illustrates the index patterns with an example of an input stream of signals with 4 samples per input and an FFT size of 4096 (which means M equals 1024).

Index pattern Description Example Comment
Continuous in/M-interval out The indexes in the FFT frame are continuous for the input data and have intervals of M for the output data, where M = FFT size/size of data in. This node uses 0, 1, 2, 3 as the indexes of the input samples in the first valid input cycle, 4, 5, 6, 7 in the second cycle, and so on. For the output samples, the indexes are 0, 1024, 2048, 3072 in the first valid output cycle, 1, 1025, 2049, 3073 in the second cycle, and so on.
M-interval in/Continuous out The indexes in the FFT frame have intervals of M for the input data and are continuous for the output data, where M = FFT size/size of data in. The indexes of the input and output are reversed compared with the Continuous in/M-interval out index pattern.

If the data source is an FPGA I/O with multiple samples per cycle, select the Continuous in/M-interval out index pattern. If the data source is the output of another FFT (Single Channel, Multiple Samples) node, such as when you compute the inverse of the FFT results obtained from another FFT (Single Channel, Multiple Samples) node, ensure the Input index pattern setting of this node matches the Output index pattern setting of the other FFT (Single Channel, Multiple Samples) node.

Optimizing for Accuracy, Resource Usage, or Timing

You can configure this node to optimize for accuracy, minimal resource usage, or timing in the Optimization section of the Item tab of the configuration pane.

In the Goal section, you can configure this node to optimize accuracy of the output data or minimize resource usage when determining output data word lengths. The following table provides guidance on which option to use for your specific use case.

Use Case Recommended Option Node Behavior Result
You want to optimize the accuracy of the last bits of output data at the cost of increased FPGA resource usage. Accuracy This node extends the word length of the input data to the output word length by padding zeros. All internal complex multiplication operations use this word length. Compared with the Resource usage option, the complex multipliers retain more bits and the increased log2(N)+1 bits in the output data are more accurate.
If either use case applies:
  • You want to reduce FPGA resource usage at the cost of less accurate output data.
  • The size of the data in input is 16 and FFT size is 16384 or above.
Resource usage This node increases word length stage-by-stage from input to output. Therefore, the bit width of complex multipliers also increases stage-by-stage. Compared with the Accuracy option, the bit widths of the complex multipliers and internal registers are smaller, which saves FPGA resources and potentially results in a higher FPGA clock rate at compilation time.

If this node still does not meet your accuracy, resource, or timing needs after you configure the optimization goal, you can adjust the values of Twiddle factor word length and Number of pipeline stages in butterfly to improve the performance of this node.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application


Recently Viewed Topics