Table Of Contents
Distributed Memory Generator (Clock-Driven Logic)
Version:
Last Modified: August 28, 2017
Creates area and performance optimized ROM blocks, single and dual port distributed memories, and SRL16-based memories for Xilinx FPGAs. The core supersedes the previously released LogiCORE Distributed Memory core. Use this core in all new designs for supported families wherever a distributed memory is required.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application