Table Of Contents
AXI4-Stream Combiner (Clock-Driven Logic)
Version:
Last Modified: August 28, 2017
Provides the ability to merge multiple SI streams onto one MI stream channel.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Interface: AXI4-Stream
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application