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Configurable Logic Blocks (CLBs) on an FPGA

Last Modified: February 27, 2020

A configurable logic block (CLB) is the basic repeating logic resource on an FPGA. When linked together by routing resources, the components in CLBs execute complex logic functions, implement memory functions, and synchronize code on the FPGA.

CLBs contain smaller components, including flip-flops, look-up tables (LUTs), and multiplexers.

  • Flip-Flop—A circuit capable of two stable states that represents a single bit. A flip-flop is the smallest storage resource on the FPGA. Each flip-flop in a CLB is a binary register used to save logic states between clock cycles on an FPGA circuit.
  • Look-up Table (LUT)—A collection of gates hardwired on the FPGA. An LUT stores a predefined list of outputs for every combination of inputs. LUTs provide a fast way to retrieve the output of a logic operation because possible results are stored and then referenced rather than calculated. The LUTs in a CLB can also implement FIFOs and memory items in LabVIEW.
  • Multiplexer—A circuit that selects between two or more inputs and then returns the selected input.

When you compile code to run on an FPGA target, LabVIEW implements much of the code using flip-flops, LUTs, and multiplexers.

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