Table Of Contents
DSP48 macro (Clock-Driven Logic)
Version:
Last Modified: August 28, 2017
Allows you to specify multiple operations using arithmetic expressions you define to abstract the XtremeDSP Slice configuration and simplify its dynamic operation. You can select the enumerated operations via a single port on the generated IP.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application