Clocks are periodic digital signals that drive the hardware elements inside an FPGA. Using clocks in LabVIEW allows you to specify the timing objectives of an FPGA application by controlling the execution rate of the Clock-Driven Loops within an FPGA VI.
The clock wired to each Clock-Driven Loop determines the execution time of one iteration of the logic within that loop. For example, a 40MHz clock results in one iteration every 25 nanoseconds. The timing objectives for your FPGA application are the rates at which you want to acquire data from each section of code.
Delay is the time it takes for a digital signal to travel from one flip-flop, through all of the logic within one Clock-Driven Loop, and to the next flip-flop. Every node in a Clock-Driven Loop takes a certain amount of time, known as logic delay, to execute. The combined logic delay of the nodes in the Clock-Driven Loop and the routing between them must be short enough to execute in one loop iteration at the specified clock rate. If the combined path is not short enough, LabVIEW returns a timing violation when you attempt to compile your code.
LabVIEW divides FPGA clocks into two categories:
Select clocks based on the timing objectives for your FPGA application. If your FPGA target does not have a base clock that allows you to acquire data at the rate you require for your FPGA application, scale the frequency of a base clock to create a derived clock that meets the timing objectives of the application.
The clock domain for each clock used in your application includes all of the code within one or more Clock-Driven Loops driven by that clock on the diagram.
Using Clock-Driven Loops to define multiple clock domains in FPGA VIs allows you to execute sections of your code at different clock rates to achieve separate timing objectives. You can use any base or derived clock that the corresponding FPGA target supports as a timing source for a Clock-Driven Loop in an FPGA VI.