Write to DRAM (Clock-Driven Logic)

Reference to a DRAM memory item.

The location to write data in memory on the FPGA target. The valid address range depends on the requested number of elements you specify when creating the input memory item. For example, if you specify a requested number of elements of 65536, the valid address range is 0–65535. If address exceeds the address range, the data will not be written to memory.

The data to write to the DRAM memory on the FPGA target.

Boolean value that specifies whether the next data point is valid and can be processed.

Wire output valid of an upstream node to this input to transfer data from the upstream node to this node.

Reference to a DRAM memory item.

Boolean value that indicates whether this node is ready to accept new input data.

Use Feedback Node to wire this output to ready for output of an upstream node.

Note  

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.