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Clock-Driven Logic

Last Modified: January 11, 2018

Clock-Driven Logic allows you to create code that executes in one clock cycle at the rate you specify for the Clock-Driven Loop. Because the code maps directly to resources on the FPGA when you compile and depends on the timing of the Clock-Driven Loop, Clock-Driven Logic code can only run within a Clock-Driven Loop on the diagram of a VI targeted to an FPGA.

You program using Clock-Driven Logic in two places.

  1. Within the Clock-Driven Loop directly.
  2. Within a Clock-Driven Logic document (.gcdl), or subCDL, placed within the Clock-Driven Loop.

Some nodes on the Clock-Driven Logic palette only function inside of a Clock-Driven Loop or a Clock-Driven document. If you add one of these nodes outside of the loop, the Errors and Warnings tab displays an error.

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