Table Of Contents
Open FPGA VI Reference (G Dataflow)
Opens a reference to an FPGA bitfile and FPGA target you specify or an FPGA application in simulation. This node executes the referenced bitfile or application by default.
Select a bitfile or application to reference in one of three ways depending on which mode you choose on the Item tab.
- Simulation—On the Item tab, select an FPGA application from your project to run in simulation mode on the host VI. This option is only enabled if your project includes FPGA applications.
- Deploy from project—On the Item tab, select a bitfile from your project to run on an FPGA target. This option is only enabled if your project includes bitfiles.
- Deploy from file—On the diagram, wire the path to a bitfile and a host interface to this node to run the bitfile on an FPGA target. Use this mode if you want to select a bitfile at runtime.
Programming Patterns
Transferring Data between a Target and Host Using FIFOs
host interface
Interface of the FPGA bitfile or application that this node returns a reference to. To set an interface for the FPGA reference, create a constant or control from this input, select what you created, and click Configure on the Item tab.
This input is only available if you select Deploy from file on the Item tab.
Opening an FPGA Bitfile Reference in Deploy from File Mode
If you select Deploy from file mode on the Item tab, you can select a bitfile to reference at runtime. You also need to define a host interface in order for this node to open a reference to the bitfile.
- Right-click the host interface input and select Create constant or Create control.
- Select the constant or control you just created and click Configure on the Item tab.
- Click either Import bitfile or Import bitfile application to load the interface from the bitfile you choose. The interface consists of resources in a bitfile, such as controls, indicators, FIFOs, and target-specific methods.
RIO address
Address of the FPGA target on which you want to run the FPGA VI. If you set this node to simulation mode, the node ignores this input.
bitfile path
run?
A Boolean that determines whether the FPGA VI executes immediately after the node opens a reference to the VI. In most scenarios, wire a False constant to this input to make sure the FPGA VI resets properly after each execution.
| True | The FPGA VI executes when the node opens a reference to it. |
| False | The FPGA VI does not execute when the node opens a reference to it. Use Download FPGA VI and Run FPGA VI to explicitly download and run the VI. This action ensures that the FPGA VI is properly reset by replacing the code on the FPGA before each execution of the VI. |
Default: true
error in
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Default: No error
reference out
A reference to an FPGA VI.
error out
Error information.
The node produces this output according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application