Table Of Contents

Open FPGA VI Reference (G Dataflow)

Last Modified: June 1, 2017

Opens a reference to the build specification or bitfile associated with an FPGA VI and the FPGA target you specify.


You cannot run an FPGA VI simulation on a real-time host.


RIO address

Name of the FPGA target on which you want to run the FPGA VI. If you run the FPGA VI in simulation on the host, LabVIEW ignores this input.



A Boolean that specifies whether the FPGA VI executes immediately after the reference to the VI is opened.

True The FPGA VI executes when the reference is opened.
False The FPGA VI does not execute when the reference is opened. Use Download FPGA VI and Run FPGA VI to explicitly download and run the VI. This action ensures that the FPGA VI is properly reset by replacing the code on the FPGA before each execution of the VI.

Default: true


error in

Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.

Default: No error


reference out

A reference to an FPGA VI.


error out

Error information. The node produces this output according to standard error behavior.

Simulating an FPGA VI on the Host

To simulate an FPGA VI on the host, select a build specification associated with the FPGA VI in the Properties group of the Configure tab.

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported

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