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Directed Optimization of FPGA VIs

Last Modified: March 30, 2016

Directed optimization of FPGA VIs allows you to notify the compiler that you want specific code to meet certain performance and resource criteria, also known as directives. The compiler then makes optimizations to try to meet the performance and resource directives you set. Algorithms are an example of code that you might want to reach a specific level of performance because of the nature of their calculations and the amount of data they are likely processing.

To indicate to the compiler that you want the code within an FPGA VI optimized to meet performance and resource directives, you set the build output for the FPGA VI in SystemDesigner to Optimized FPGA VI.

The optimizations the compiler can make are directly affected by the code you want to optimize. Keep the following considerations in mind when creating Optimized FPGA VIs:

  • The editor changes in an effort to help you create code that is more easily optimized by the FPGA compiler.
    • You have access to a subset of G Dataflow nodes, primarily those related to performing mathematical calculations.
    • The editor displays warnings or errors if aspects of your algorithms won't function on the FPGA target.
    • You have access to tools that help you estimate the performance your algorithm can achieve and the FPGA resources your algorithms require prior to compiling the code on the FPGA.
  • Reducing the complexity of the code and using values that the compiler can determine before run time provide the compiler with the best opportunity to optimize your code.
  • There are programming patterns that affect the performance of code in Optimized FPGA VIs, and there are constructs you should avoid in order to achieve the maximum possible performance.

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