Creating Custom Condition Symbols for a Top-Level FPGA VI

You can create custom condition symbols targeted to a top-level FPGA VI and use these symbols in any Disable Structure within your FPGA application.

Before you begin, you must designate a top-level FPGA VI in your application. Refer to Designating a Top-Level FPGA VI for more information.

1. In SystemDesigner, select the top-level FPGA VI in your application.
2. On the Item tab, in the Compile Symbols section, click the plus button to create a new symbol.
3. Enter a name and value for the symbol. Choose a name that indicates what the condition symbol is evaluating.

You can now select the symbol you created in a Disable Structure in any document in your application.