To run code on an FPGA, you must compile the top-level FPGA VI and its referenced documents into a bitfile that you then deploy to the FPGA. The bitfile transfers all the code and performance requirements of an application to an FPGA target.
Complete the following steps to begin compiling a bitfile:
Do not change any code in your FPGA VI during the diagram analysis stage of compilation. Any changes you make to code during the diagram analysis stage may be reflected in the bitfile. If you want to continue working on code while you wait for the compilation to finish, do so after the diagram analysis stage.