Table Of Contents
Adder Subtracter (Clock-Driven Logic)
Version:
Last Modified: August 28, 2017
Creates adders, subtracters, and adders/subtracters that operate on signed or unsigned data. In fabric, the module supports inputs ranging from 1 to 256 bits wide, and outputs ranging from 1 to 258 bits wide. I/O widths are family dependent for DSP48 implementations.
In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application