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Provides support for NI data acquisition and signal conditioning devices.
Provides support for Ethernet, GPIB, serial, USB, and other types of instruments.
Provides support for NI GPIB controllers and NI embedded controllers with GPIB ports.
Writes elements to the DMA FIFO from the host VI.
Reference to an FPGA VI.
Data specifies the value(s) you would like to transfer to the FPGA target.
Timeout (ms) specifies the minimum number of milliseconds the DMA write function waits before timing out.
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Default: no error
Empty elements remaining returns the number of empty elements available for writing in the host-side DMA channel buffer.
The node produces this output according to standard error behavior.
Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported
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