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Resolving Timing Violations on the FPGA

Timing violations occur when sections of code require more time to execute than the time required by the code in your build specification, or build spec. The compilation for a build spec must be free of errors before you run the code on the FPGA. After you compile a build spec for an FPGA target, LabVIEW displays timing-related errors that occur during compilation, or timing violations, in the compilation status report.

Resolve timing violations using the following steps.

  1. Access the compilation status report by double-clicking a build spec in the Compilation Status pane.
  2. In the Build Errors section of the compilation status report, click Investigate to view timing violations in your build spec. The Timing Violations pane displays a row for each section of your code that failed to meet the timing requirements specified by your build spec. Each section of your code that contains timing errors is called a critical path. When possible, the Timing Violations pane reports timing violations for individual objects inside of a critical path. The following image shows how LabVIEW displays timing violations in the Timing Violations pane.
  3. Double-click each critical path or object in the Timing Violations pane to highlight the critical path or object on the diagram. Update critical paths with the longest timing delays first using the following strategies.

    You can recompile your build spec after implementing each strategy to test the impact of your code revisions on the original timing violations.

    • Reduce long node paths inside each Clock-Driven Loop.

      Each node takes a certain amount of time to execute, so use fewer nodes inside each Clock-Driven Loop by simplifying the logic of the code, if possible. Long node paths inside a Clock-Driven Loop result in timing delays when compiled on the FPGA. Also, avoid deeply nested Case Structures to reduce the length of paths inside a Clock-Driven Loop.

    • Use pipelining.

      Pipelining is the process of restructuring one long section of code into several shorter sections that run in parallel. Pipelining takes advantage of the parallel processing capabilities of the FPGA to increase efficiency of sequential code.

      To implement pipelining, divide code into discrete steps and wire the inputs and outputs of each step to Feedback Nodes in the Clock-Driven Loop. The following image shows code organized into subCDLs and pipelined through Feedback Nodes.

    • Use smaller data types.

      Use the smallest data type possible for terminals to decrease the size and increase the speed of an FPGA VI. For example, if a terminal uses a 32-bit integer data type by default, but you know the terminal will never contain a number above 255, change the data type of the terminal to an 8-bit integer to use fewer FPGA resources.

    • Reduce the clock rate of Clock-Driven Loops that contain critical paths.

      If your application does not explicitly depend on completing each clock cycle at exactly the rate specified, reduce the frequency of the clock that drives the components that failed to meet timing requirements.

    • Recompile the build spec.

      If your failed compilation misses the required throughput time by only a few nanoseconds, try recompiling your build spec. Each compilation of a build spec does not always produce identical results on the FPGA, so recompiling a build spec sometimes resolves minor timing violations.

      If your build spec continues to return timing violations, repeat the previous strategies. If you cannot eliminate timing violations, consider moving parts of your application to the host processor.

Resolving Optimized or Non-Diagram Logic Timing Violations

The Timing Violations pane reports errors under Optimized or Non-Diagram Logic whenever LabVIEW cannot determine the location of the timing violation in the compiled code. Timing violations for Clock-Driven Logic code, Multirate Diagram code, and FPGA IP code often appear under Optimized or Non-Diagram Logic in the Timing Violations pane.

Choose the following strategy to resolve optimized or non-diagram logic timing violations, based on the type of code you include in the build spec.
  • For Clock-Driven Logic code, use the strategies listed in Resolving Timing Violations on the FPGA.

    The compiler often implements common operations (i.e. Add, Multiply) in dedicated resource blocks to optimize the performance of the code. As a result, part of your critical path from a Clock-Driven Logic document or a Clock-Driven Loop often appears under Optimized or Non-Diagram Logic.

  • For Multirate Diagram code, revise the Design Properties configuration.

    On the Multirate Diagram tab, decrease the Clock Rate and increase the Pipelines for the code to improve timing.

  • For FPGA IP code, revise the FPGA Estimates configuration.

    On the VI tab, select FPGA Estimates and increase the Routing Margin and Clock Rate to improve the timing in the code. If the Optimized or Non-Diagram Logic object still shows a large delay after you revise the FPGA Estimates configuration, try revising your FPGA IP algorithm. Verify that the clock rate you requested for your FPGA IP algorithm matches the clock rate of the Clock-Driven Loop or Clock-Driven Logic document that calls the FPGA IP algorithm.


If you are familiar with text-based FPGA compilation error reports, you can locate the full text reports for your compilation in the following location on disk: C:\NIFPGA\compilation\<your_compilation>\ccout