If the FPGA target base clocks fail to execute code at a rate that meets the timing objectives of your application, you can create a derived clock to achieve faster execution rates.
Complete the following steps to create and use a derived clock in LabVIEW.
In SystemDesigner, double-click the Clocks category of the FPGA target Home Page.
Add a new clock to the FPGA target and make your selections in the New Derived Clock dialog box.
If your entry falls outside the range of the slider, LabVIEW automatically adjusts your entry to the closest acceptable number.
|Set by Frequency
||Use this method if you know the timing objective of your code according to the frequency, measured in MHz.
|Set by Period
||Use this method if you know the timing objective of your code according to the length of one period, measured in ns.
Optional: Rename the clock to more easily differentiate between clocks on the diagram. By default, the name is DerivedClock.
Use the derived clock to drive a Clock-Driven Loop and control the timing of your code on the FPGA. You can select a derived clock from a clock constant in an FPGA VI or Clock-Driven Logic document.