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An FPGA VI is a VI that you target to an FPGA.

The following example shows the FPGA VI on an FPGA target in SystemDesigner.

You designate a single FPGA VI as the top-level VI on the FPGA and it serves as the container for your overall FPGA application. Place all of the code that makes up your FPGA application either on the diagram of the FPGA VI directly or within subdocuments that appear on the diagram of the FPGA VI. This code can include Clock-Driven Logic, FPGA IP, and Multirate Dataflow code. You compile a build specification for the top-level FPGA VI, so any code referenced within that VI compiles as part of the FPGA application.

Because the resources available to a program running on an FPGA differ from those available on the host, an FPGA VI includes only palette objects and data types that are compatible with an FPGA. For example, the palette in an FPGA VI displays nodes and terminals that receive or generate FPGA resource references, such as the Multirate Diagram language integration node and clock, I/O, and memory item references. The palette in an FPGA VI also includes the Clock-Driven Loop, which you place around the majority of the code on the diagram to control the execution speed of that code on the FPGA.


Search LabVIEW for the following installed lessons: Programming with Clock-Driven Logic