Designating a Top-Level FPGA VI

To communicate with an FPGA VI from the host computer, the FPGA VI must be designated as a top-level VI.

When you create a new top-level VI on an FPGA in SystemDesigner, LabVIEW automatically creates a build specification for the FPGA VI and bolds the VI name in SystemDesigner. The bold VI name in SystemDesigner is a visual indicator that the VI is a top-level VI.

If you create a VI that is not a top-level VI and later decide you want it to be your top-level FPGA VI, you must manually specify it as such.

1. In SystemDesigner, double-click the Source Code category of the FPGA target Home Page.
2. Select the VI you want to designate as the top-level VI.
3. On the Configure tab, select Mark as Top-Level. LabVIEW automatically generates a build specification for a VI designated as a top-level VI.