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A FIFO is a data structure that holds elements in the order they are received and provides access to those elements using a first-in, first-out basis.

The following illustration demonstrates the behavior of elements moving through a FIFO.

The type of FIFO you create depends on the way you need to transfer data.

Type of Data Transfer Type of FIFO Considerations
Between Clock-Driven Loops Local FIFO

You can access local FIFOs created through SystemDesigner across documents in your project. However, to share the documents that reference that FIFO with another user, you must send the entire project.

To create individual FPGA VIs that you can send to other users, use Create FIFO to create a local FIFO within the VI.

Between the host processor and the FPGA Direct Memory Access (DMA) FIFO Use DMA FIFOs instead of controls and indicators on the FPGA VI for better performance, when communicating between a host processor and an FPGA VI. A DMA FIFO allocates memory on both the host computer and the FPGA target yet acts as a single FIFO, to take advantage of the resources of each device.
Between two FPGA targets or between an FPGA and non-FPGA target Peer-to-Peer FIFO FIFOs must read or write one sample at a time, so avoid sending simultaneous read or write requests from different hardware targets to a single FIFO.
From the FPGA to external memory Dynamic RAM (DRAM) FIFO

DRAM FIFOs allow you to transfer data without sending data through the host processor. You can use DRAM FIFOs for data logging when the FPGA target is not continuously connected to a host, like in many embedded applications. You can configure a DRAM FIFO to create data ports up to the size of the entire DRAM memory bank.

In LabVIEW, you must construct a DRAM FIFO using a DRAM memory item and registers. Search LabVIEW for the following example of DRAM FIFOs: Simple External Memory FIFO.