Home > Support > NI Product Manuals > LabVIEW Communications System Design Suite 1.0 Manual

Clock-Driven Logic allows you to create code that executes in one clock cycle at the rate you specify for the Clock-Driven Loop.

You program using the Clock-Driven Logic language in two places:

  • Within a Clock-Driven Logic document (.gcdl)
  • Within a VI targeted to an FPGA (.gvi), after you place a Clock-Driven Loop on the diagram

You place a Clock-Driven Logic document, or subCDL, within the Clock-Driven Loop on the diagram of a top-level VI targeted to an FPGA. You can use the Clock-Driven Loop within the top-level FPGA VI to implement multiple clock domains on an FPGA and optimize the performance of your code.