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Implements a fully synchronous Viterbi decoder, using a single clock.Options include parameterizable constraint length, convolutional codes, and traceback length. You can use various architectures including parallel, serial, multi-channel, and dual decoding. The core is delivered through the Xilinx CORE Generator System and integrates with the Xilinx design flow.

Need License: Yes

Interface: AXI4-Stream


Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices