These specifications apply to the PCI-6561 with 2 MBit, 16 MBit, and 128 MBit of memory per channel.
Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.
The following characteristic specifications describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
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Channels |
Data DDC CLK OUT PFI <0..3> |
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LVDS[2] | LVCMOS | LVPECL[3] | |||
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Offset (Vos) | Differential Voltage (Vod) | Low | High | Single Ended Output Low | Single Ended Output High |
1.125 V, min | 247 mV, min | 0.2 V, max | 2.8 V, min | 1.38 V, min | 2.16 V, min |
1.220 V, typ | 305 mV, typ | — | — | 1.72 V, max | 2.50 V, max |
1.375 V, max | 454 mV, max | — | — | — | — |
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Data channel driver enable/disable control |
Software-selectable: per channel |
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Channel power-on state[4] |
Drivers disabled, 100 Ω differential impedance PFI 3: LVDS mode |
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Channels |
Data STROBE PFI <0..3> |
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Sources |
1. On Board clock (internal voltage-controlled crystal oscillator [VCXO] with divider) 2. CLK IN (SMB jack connector) 3. STROBE (DDC connector; acquisition only) |
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Channels |
Data DDC CLK OUT PFI <0..3> |
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Data channel-to-channel skew[11] |
±215 ps, typical ±500 ps, maximum |
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Data position modes |
Sample clock rising edge Sample clock falling edge Delay from Sample clock rising edge |
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Compare the setup and hold times from the datasheet of the of your device under test (DUT) to the values in the preceding specifications. The provided setup and hold times must be greater than the setup and hold times required for the DUT. If you require more setup time, configure your exported Sample clock mode as Inverted and/or delay your data relative to the Sample clock.
The Transition time and Sample clock specification values assume that the Data Position is set to the rising edge of the Sample clock and that the Sample clock is exported to the DDC connector. These values include the worst-case effects of channel-to-channel skew, inter-symbol interference, and jitter.
Channels |
Data STROBE PFI <0..3> |
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Data position modes |
Sample clock rising edge Sample clock falling edge Delay from Sample clock rising edge |
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Connector |
SMB jack |
Direction |
Input |
Destinations |
1. Reference clock for the phase-locked loop (PLL) 2. Sample clock |
Input coupling |
AC |
Input protection |
±10 VDC |
Input impedance |
Software-selectable: 50 Ω (default) or 1 kΩ |
Minimum detectable pulse width |
2 ns |
Clock requirements |
Free-running (continuous) clock |
Voltage Range (Vpk-pk) | Sine Wave | Square Wave | |
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Frequency Range | Frequency Range | Duty Cycle | |
0.65 to 5.0 | 5.5 MHz to 100 MHz | 20 kHz to 100 MHz | ƒ <50 MHz: 25% to 75% ƒ ≥50 MHz: 40% to 60% |
1.0 to 5.0 | 3.5 MHz to 100 MHz | — | — |
2.0 to 5.0 | 1.8 MHz to 100 MHz | — | — |
Frequency range |
10 MHz ±50 ppm |
Voltage range |
0.65 Vpk-pk to 5.0 Vpk-pk |
Duty cycle |
25% to 75% |
Connector |
DDC |
Direction |
Input |
Destination |
Sample clock (acquisition only) |
Frequency range |
48 Hz to 100 MHz |
Duty cycle range |
ƒ <50 MHz: 25% to 75% ƒ ≥50 MHz: 40% to 60% |
Minimum detectable pulse width |
2 ns |
Clock requirements |
Free-running (continuous) clock |
Input impedance |
100 Ω differential[18] |
Connector |
SMB jack |
Direction |
Output |
Sources |
1. Sample clock (excluding STROBE) 2. Reference clock (PLL) |
Output impedance |
50 Ω, nominal |
Logic type |
LVCMOS |
Maximum drive current |
32 mA |
Connector |
DDC |
Direction |
Output |
Source[19] |
Sample clock (excluding STROBE) |
Logic types |
LVDS LVPECL |
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Transition time |
1 ns |
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Output impedance |
100 Ω differential |
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Sources[23] |
1. RTSI 7 2. CLK IN (SMB jack connector) 3. None (On Board clock not locked to a reference) |
Destination |
CLK OUT (SMB jack connector) |
Lock time |
400 ms, typical |
Frequencies |
10 MHz ±50 ppm |
Duty cycle range |
25% to 75% |
Memory architecture |
The PCI-6561 uses Synchronization and Memory Core (SMC) technology in which waveforms and instructions share onboard memory. Parameters such as number of script instructions, maximum number of script instructions, maximum number of waveforms in memory, and number of samples (S) available for waveform storage are flexible and user defined. |
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Configuration | Sample Rate |
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100 MHz | |
Single waveform | 4 S |
Continuous waveform | 32 S |
Stepped sequence | 128 S |
Burst sequence | 512 S |
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Trigger Types | Sessions | Edge Detection | Level Detection |
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1. Start | Acquisition and generation | Rising or falling | — |
2. Pause | Acquisition and generation | — | High or low |
3. Script <0..3> | Generation | Rising or falling | High or low |
4. Reference | Acquisition | Rising or falling | — |
5. Advance | Acquisition | Rising or falling | — |
Sources |
1. PFI 0 (SMB jack connector) 2. PFI <1..3> (DDC connector) 3. RTSI <0..7> (RTSI bus) 4. Pattern match (acquisition sessions only) 5. Software (user function call) 6. Disabled (do not wait for a trigger) |
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Destinations[29] |
PFI 0 (SMB jack connectors) PFI <1..3> (DDC connector) RTSI <0..6> (RTSI bus) |
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Trigger Operation | Samples, Typical | Samples, Maximum |
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Start to Reference | 85 S | 96 S |
Start to Advance | 220 S | 230 S |
Reference to Reference | 210 S | 230 S |
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Delay from trigger to digital data output |
34 Sample clock periods + 85 ns |
Warm-up time |
15 minutes |
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Driver support for this device was first available in NI-HSDIO 1.3.
NI-HSDIO is an IVI-compliant driver that allows you to configure, control, and calibrate the PCI-6561. NI-HSDIO provides application programming interfaces for many development environments.
VDC | Current Draw, Maximum |
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+3.3 V | 1.7 A |
+5 V | 1.1 A |
+12 V | 0.4 A |
-12 V | 0.05 A |
Total power |
16.5 W, maximum |
Dimensions |
12.6 cm × 35.5 cm (4.96 in × 13.9 in) |
Weight |
410 g (14.5 oz) |
Label | Connector Type | Description |
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CLK IN | SMB jack | External Sample clock, external PLL reference input |
PFI 0 | Events, triggers | |
CLK OUT | Exported Sample clock, exported Reference clock | |
DIGITAL DATA & CONTROL | 12X InfiniBand connector | Digital data channels, exported Sample clock, STROBE, events, triggers |
The SHB12X-B12X LVDS cable, NI part number 192344-01, is a pass-through cable. When designing a custom fixture, notice that the cable pinout is reversed from that of the PCI-6561. For example, the PCI-6561 generates DIO 0 on pin 14. This signal connects to pin 60 at the cable end. Refer to the NI Digital Waveform Generator/Analyzer Getting Started Guide or the NI Digital Waveform Generator/Analyzer Help at ni.com/manuals for more pinout information.
To ensure that the PCI-6561 cools effectively, follow the guidelines in the Maintain Forced Air Cooling Note to Users included with the PCI-6561 or available at ni.com/manuals. The PCI-6561 is intended for indoor use only.
Operating temperature |
0 °C to 45 °C |
Operating relative humidity |
10 to 90% relative humidity, noncondensing (meets IEC 60068-2-56) |
Storage temperature |
-20 °C to 70 °C (meets IEC 60068-2-2) |
Storage relative humidity |
5 to 95% relative humidity, noncondensing (meets IEC 60068-2-56) |
Altitude |
0 to 2,000 m above sea level (at 25 °C ambient temperature) |
Pollution degree |
2 |
This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:
For UL and other safety certifications, refer to the product label or the Online Product Certification section.
For EMC declarations, certifications, and additional information, refer to the Online Product Certification section.
To meet EMC compliance, the following cautions apply:
This product meets the essential requirements of applicable European Directives, as follows:
Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.
NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.
For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.
At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.