These specifications apply to the PCI-6551 with 1 MBit, 8 MBit, and 64 MBit of memory per channel.
Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.
The following characteristic specifications describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
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Channels |
Data DDC CLK OUT PFI <0..3> |
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Signal type |
Single-ended |
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Total programmable voltage levels[1] |
1 voltage low level 1 voltage high level |
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Data channel driver enable/disable control |
Per channel Per cycle |
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Channel power-on state[3] |
Drivers disabled, 50 kΩ input impedance |
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Channels |
Data STROBE PFI <0..3> |
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Voltage comparators per channel |
2 |
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Total programmable thresholds[4] |
1 voltage low threshold 1 voltage high threshold |
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Voltage range |
-2.0 V to 5.5 V |
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Input impedance[7] |
50 Ω nominal or 50 kΩ (default) |
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Input protection range[8] |
-2.3 V to 6.8 V |
Sources |
1. On Board clock (internal voltage-controlled crystal oscillator [VCXO] with divider) 2. CLK IN (SMB jack connector) 3. STROBE (DDC connector; acquisition only) |
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Channels |
Data DDC CLK OUT PFI <0..3> |
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Data channel-to-channel skew |
±300 ps, typical ±900 ps, maximum |
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Maximum data channel toggle rate |
25 MHz |
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Data format |
Non-return to zero (NRZ) |
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Data position modes |
Sample clock rising edge Sample clock falling edge Delay from Sample clock rising edge |
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Exported Sample clock offset (tCO) |
Software-selectable: 0 ns or 2.5 ns (default) |
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Time delay from Sample clock (internal) to DDC connector (tSCDDC) |
32.5 ns, typical |
Channels |
Data STROBE PFI <0..3> |
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Channel-to-channel skew |
±400 ps, typical ±900 ps, maximum |
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Data position modes, per channel |
Sample clock rising edge Sample clock falling edge Delay from Sample clock rising edge |
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Minimum detectable pulse width[12] |
4 ns |
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Time delay from DDC connector data to internal Sample clock (tDDCSC) |
27.5 ns, typical |
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Connector |
SMB jack |
Direction |
Input |
Destinations |
1. Reference clock for the phase-locked loop (PLL) 2. Sample clock |
Input coupling |
AC |
Input protection |
±10 VDC |
Input impedance |
Software-selectable: 50 Ω (default) or 1 kΩ |
Minimum detectable pulse width[15] |
4 ns |
Clock requirements |
Free-running (continuous) clock |
Voltage Range (Vpk-pk) | Sine Wave | Square Wave | |
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Frequency Range | Frequency Range | Duty Cycle | |
0.65 to 5.0 | 5.5 MHz to 50 MHz | 20 kHz to 50 MHz |
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1.0 to 5.0 | 3.5 MHz to 50 MHz | — | — |
2.0 to 5.0 | 1.8 MHz to 50 MHz | — | — |
Frequency range |
10 MHz ±50 ppm |
Voltage range |
0.65 Vpk-pk to 5.0 Vpk-pk |
Duty cycle |
25% to 75% |
Connector |
DDC |
Direction |
Input |
Destinations |
Sample clock (acquisition only) |
Frequency range |
48 Hz to 50 MHz |
Duty cycle range[16] |
25% to 75% |
Minimum detectable pulse width[17] |
4 ns |
Voltage thresholds |
Refer to Acquisition Timing in the Timing section. |
Clock requirements |
Free-running (continuous) clock |
Input impedance[18] |
Software-selectable: 50 Ω or 50 kΩ (default) |
Connector |
SMB jack |
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Direction |
Output |
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Sources |
1. Sample clock (excluding STROBE) 2. Reference clock (PLL) |
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Output impedance |
50 Ω, nominal |
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Connector |
DDC |
Direction |
Output |
Source[19] |
Sample clock |
Electrical characteristics |
Refer to Generation Timing in the Timing section. |
Sources[20] |
1. RTSI 7 2. CLK IN (SMB jack connector) 3. None (On Board clock not locked to a reference) |
Destination |
CLK OUT (SMB jack connector) |
Lock time |
400 ms, typical |
Frequencies |
10 MHz ±50 ppm |
Duty cycle range |
25% to 75% |
Memory architecture |
The PCI-6551 uses Synchronization and Memory Core (SMC) technology in which waveforms and instructions share onboard memory. Parameters such as number of script instructions, maximum number of script instructions, maximum number of waveforms in memory, and number of samples (S) available for waveform storage are flexible and user defined. |
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Configuration | Sample Rate |
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50 MHz | |
Single waveform | 2 S |
Continuous waveform | 16 S |
Stepped sequence | 64 S |
Burst sequence | 256 S |
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Trigger Types | Sessions | Edge Detection | Level Detection |
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1. Start | Acquisition and generation | Rising or Falling | — |
2. Pause | Acquisition and generation | — | High or Low |
3. Script <0..3> | Generation | Rising or Falling | High or Low |
4. Reference | Acquisition | Rising or Falling | — |
5. Advance | Acquisition | Rising or Falling | — |
Sources |
PFI 0 (SMB jack connector) PFI <1..3> (DDC Connector) RTSI <0..7> (RTSI bus) Pattern match (acquisition sessions only) Software (user function call) Disabled (do not wait for a trigger) |
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Destinations[26] |
PFI 0 (SMB jack connectors) PFI <1..3> (DDC connector) RTSI <0..6> (RTSI bus) |
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Trigger Operation | Samples, Typical | Sample, Maximum |
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Start to Reference | 57 S | 64 S |
Start to Advance | 138 S | 143 S |
Reference to Reference | 132 S | 153 S |
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Delay from trigger to digital data output |
32 Sample clock periods + 160 ns |
Types | Sessions |
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1. Marker <0..3> | Generation |
2. Data Active | Generation |
3. Ready for Start | Acquisition and generation |
4. Ready for Advance | Acquisition |
5. End of Record | Acquisition |
6. Sample Error | Hardware comparison |
7. Delayed Data Active | Hardware comparison |
Destinations[28] |
1. PFI 0 (SMB jack connector) 2. PFI <1..3> (DDC connector) 3. RTSI <0..7> (RTSI bus) |
Marker time resolution (placement) |
Markers must be placed at an integer multiple of 2 S (samples). |
Interval for external calibration |
2 years |
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Warm-up time |
15 minutes |
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Driver support for this device was first available in NI-HSDIO 1.0.
NI-HSDIO is an IVI-compliant driver that allows you to configure, control, and calibrate the PCI-6551. NI-HSDIO provides application programming interfaces for many development environments.
VDC | Current Draw, Typical | Current Draw, Maximum |
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+3.3 V | 2.0 A | 2.0 A |
+5 V | 1.8 A | 2.4 A |
+12 V | 0.3 A | 0.5 A |
-12 V | 0.2 A | 0.2 A |
Total power |
21.6 W, typical 27 W, maximum |
Dimensions |
12.6 cm × 35.5 cm (4.95 in × 13.9 in) |
Weight |
375 g (13.2 oz) |
Label | Connector Type | Description |
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CLK IN | SMB jack | External Sample clock, external PLL reference input |
PFI 0 | Events, triggers | |
CLK OUT | Exported Sample clock, exported Reference clock | |
DIGITAL DATA & CONTROL | 68-pin VHDCI connector | Digital data channels, exported Sample clock, STROBE, events, triggers |
To ensure that the PCI-6551 cools effectively, follow the guidelines in the Maintain Forced Air Cooling Note to Users included with the PCI-6551 or available at ni.com/manuals. The PCI-6551 is intended for indoor use only.
Operating temperature |
0 °C to 45 °C |
Operating relative humidity |
10 to 90% relative humidity, noncondensing (meets IEC 60068-2-56) |
Storage temperature |
-20 °C to 70 °C (meets IEC 60068-2-2) |
Storage relative humidity |
5 to 95% relative humidity, noncondensing (meets IEC 60068-2-56) |
Altitude |
0 to 2,000 m above sea level (at 25 °C ambient temperature) |
Pollution degree |
2 |
This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:
For UL and other safety certifications, refer to the product label or the Online Product Certification section.
For EMC declarations, certifications, and additional information, refer to the Online Product Certification section.
To meet EMC compliance, the following cautions apply:
This product meets the essential requirements of applicable European Directives, as follows:
Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.
NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.
For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.
At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.