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Discrepancy Time (Digital Configurations)

    Last Modified: May 15, 2018

    Discrepancy time defines the delay before the User Program checks whether the signals are complementary or equivalent, based on your configuration.

    Figure 1. Discrepancy Time

    Dual input configurations introduce additional discrepancy due to signal routing and counter timebases. This results in a maximum tolerable discrepancy which is shorter than the configured parameter by the amount of an FPGA-based minimum discrepancy timer.

    Maximum tolerable discrepancy = discrepancy time - minimum discrepancy timer

    Refer to the following table to calculate the minimum discrepancy timer values based on the configuration.

    Table 1. Calculating Minimum Discrepancy Timer Values
    Debounce Filter Time Dual Input Dual Input with Test Pulse
    0 μs < debounce filter time50 μs 100 μs
    50 μs < debounce filter time 2 × debounce filter time (2 × debounce filter time) + test pulse width

    You cannot set debounce filter time < 108 μs when using dual input with test pulse.

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