Discrepancy time defines the delay before the User Program checks whether the signals are complementary or equivalent, based on your configuration.
Dual input configurations introduce additional discrepancy due to signal routing and counter timebases. This results in a maximum tolerable discrepancy which is shorter than the configured parameter by the amount of an FPGA-based minimum discrepancy timer.
Maximum tolerable discrepancy = discrepancy time - minimum discrepancy timer
Refer to the following table to calculate the minimum discrepancy timer values based on the configuration.
|Debounce Filter Time||Dual Input||Dual Input with Test Pulse|
|0 μs < debounce filter time ≤ 50 μs||100 μs||—|
|50 μs < debounce filter time||2 × debounce filter time||(2 × debounce filter time) + test pulse width|