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Write FIFO (Write U128 FIFO) (Clock-Driven Logic)

Version:
    Last Modified: August 4, 2018

    Writes data to a 128-bit FIFO. This node is a wrapper around the LabVIEW FPGA FIFO Write method and exposes handshaking signals that indicate when the FIFO is ready to accept new data.

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    fifo

    Reference to a FIFO.

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    reset

    Boolean signal that resets the handshaking logic directly in front of the LabVIEW FPGA FIFO Write method. This parameter does not reset the entire FIFO. To reset the entire FIFO, assert the reset signal and call the LabVIEW FPGA FIFO Clear method. This node will not write data to the FIFO if this parameter is True.

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    input data

    Data to write to the FIFO.

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    high

    Higher 64 bits of the 128-bit data to write to the FIFO.

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    low

    Lower 64 bits of the 128-bit data to write to the FIFO.

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    input valid

    Boolean value that specifies whether the input data is valid during the current clock cycle. This node will not write to the FIFO if this value is False.

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    ready for input

    Boolean value that indicates whether this node is ready to write new data to the FIFO in the next clock cycle.

    Where This Node Can Run:

    Desktop OS: none

    FPGA: Supported

    Web Server: Not supported in VIs that run in a web application


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