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Synchronous Latch (Clock-Driven Logic)

Version:
    Last Modified: August 4, 2018

    Stores information about the previous True values of the signal. You can reset this node to search for another True value of the same signal.

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    set

    Boolean value that specifies whether to set the internal state of the node to True.

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    clear

    Boolean value that specifies whether to set the internal state of the node to False.

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    out

    Internal state retained within the node. The value of this parameter is False when clear is True, True when set is True and clear is False, and remains unchanged from its previous value when both clear and set are False.

    Where This Node Can Run:

    Desktop OS: none

    FPGA: Supported

    Web Server: Not supported in VIs that run in a web application


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