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Read FIFO (Read Boolean FIFO) (Clock-Driven Logic)

    Last Modified: July 18, 2018

    Reads data from a Boolean FIFO. This node is a wrapper around the LabVIEW FPGA FIFO Read method and exposes handshaking signals to control when data is read from the FIFO.



    Reference to a FIFO.


    ready for output

    Boolean value that specifies whether the consumer of the data read from the FIFO is ready to accept new data.

    True Indicates the consumer is ready to accept new data and this node is allowed to read data from the FIFO.
    False Prevents this node from returning new data.

    output data

    Data read from the FIFO.


    output valid

    Boolean value that indicates whether the data read from the FIFO is valid during the current clock cycle.

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: Supported

    Web Server: Not supported in VIs that run in a web application

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