Table Of Contents
Detect Rising Edge (Clock-Driven Logic)
Version:
Last Modified: August 4, 2018
Detects a transition from False to True on the input signal. Use Detect Rising Edge inside a Clock-Driven Loop.
signal
Signal on which to detect a transition.
edge detected
Boolean value that indicates whether this node has detected the transition on the input signal.
Where This Node Can Run:
Desktop OS: none
FPGA: Supported
Web Server: Not supported in VIs that run in a web application