Table Of Contents
D Latch (D Latch U64) (Clock-Driven Logic)
Version:
Last Modified: August 4, 2018
Latches the input data until it is cleared.
s
Boolean value that specifies whether to copy the value of d to q.
d
The data to be latched.
r
Boolean value that specifies whether to reset q to 0.
q
Copy of the value of d after it is cleared.
Where This Node Can Run:
Desktop OS: none
FPGA: Supported
Web Server: Not supported in VIs that run in a web application