RTG Coprocessor Link v1 FPGA.lvlib

The library includes common functionality that most Coprocessor applications require:

Create Resources VI—A required constructor for the RTG Coprocessor Link class.

Read Data Stream VI—Reads data from the VST. Data arrives in blocks of multiple samples per clock allowing it to process up to 2.5 GS/s at clock rates that can be successfully compiled. Data is not valid on every clock as this loop runs slightly faster than the VST clock to overcome required Aurora protocol overhead.

Write Data Stream VI—Sends data to the VST. Like Read Data Stream VI, this VI processes data in 8SPC blocks. In the example, the write block’s ‘ready for output’ block is ignored. This is because, as the code is designed, all data is gated by the data read from the VST. The VST can read and write at the same throughput, which means if the exact same amount of data that is read from the VST (and nothing additional) is written back to the VST, the system stays in balance preventing data over/underflows.

Process VI—Performs all Aurora communication in a separate timed loop. This code performs the low-level interactions with the Aurora protocol and sends data to/from the read/write VIs.

Create Address Space Collection VI—Builds the address spaces that are added to the Instruction Framework used to communicate with the host.

Read Register VI—Provides access to the host facing registers of reset and enable.