Use an FPGA I/O Node configured for reading and writing with this device.

Use the FPGA I/O Node to access the following terminals for this device.

Table 639. Terminals in Software
Terminal Description
Connector0/AIx Analog input channel x, where x is the number of the channel. The sbRIO-9637 has AI channels 0 to 15.
Connector0/AOx Analog output channel x, where x is the number of the channel. The sbRIO-9637 has AO channels 0 to 3.
Connectorx/DIOy Digital input/output channel y on connector x, where y is the channel number and x is the connector number. The sbRIO-9637 has channels 0 to 27. Use the FPGA I/O Node, the Set Output Data method, or the Set Output Enable method to access this channel.

Arbitration

Configure the arbitration settings for the DIO channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate.

I/O Methods

Use the FPGA I/O Method Node to access the following I/O methods for this device.

Table 640. I/O Methods
Method Description
Set Output Data Refer to the FPGA I/O Method Node topic in the LabVIEW FPGA Module Programming Reference Manual for a description of this method.
Set Output Enable Refer to the FPGA I/O Method Node topic in the LabVIEW FPGA Module Programming Reference Manual for a description of this method.

Module Methods

This device does not support any module methods.

Module Properties

Use the FPGA I/O Property Node to access the following properties for this device.

Table 641. Module Properties
Property Description
Terminal Mode Sets the terminal mode for a channel as RSE (referenced single-ended) or DIFF (differential). This property overwrites the value you configure in the FPGA I/O Properties dialog box.
Voltage Range Sets the input range for a channel as ±10 V, ±5 V, ±2 V, or ±1 V. This property overwrites the value you configure in the FPGA I/O Properties dialog box.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop for digital I/O only. To configure the number of output synchronizing registers or input synchronizing registers for the channels on this device, use the Advanced Code Generation page of the FPGA I/O Properties dialog box.