The VRTS with 4 GHz Bandwidth requires a 10 MHz reference clock signal. NI-VRTS provides three reference clocking options: Onboard, PXIClk, and RefIn.

Note For configurations with more than one simulated object (and therefore more than one PXIe-5551 module), modules are referred to as "first" and "subsequent". For configurations with only one simulated object, the "first" PXIe-5551 refers to the only PXIe-5551.

The default reference clock for the first PXIe-5551 module is Onboard. The default reference clock for subsequent PXIe-5551 modules is RefIn.

Refer to the following configuration guidelines for each clocking option:

Table 5.
Clocking Option First PXIe-5551 Subsequent PXIe-5551
Onboard
  • Set the Reference Clock Source property to Onboard
  • Set the Active Channel property to VDG0.
  • Leave the Reference Clock Source property as default (RefIn). Chain the REF OUT port of the first PXIe-5551 module to the REF IN port of the subsequent PXIe-5551 modules.
PXIClk
  • Set the Reference Clock Source property to PXIClk.
  • Set the Active Channel property to VDG0.
  • Set the Reference Clock Source property of subsequent PXIe-5551 modules to either PXIClk or leave it as default.
  • If you leave the Reference Clock Source property as default, chain the REF OUT port of the first PXIe-5551 module to the REF IN port of the subsequent PXIe-5551 modules.
RefIn
  • Set the Reference Clock Source property to RefIn.
  • Set the Active Channel property to VDG0.
  • You must drive a valid 10 MHz reference clock signal to the first PXIe-5551 REF IN port.
  • Leave the Reference Clock Source property as default (RefIn). Chain the REF OUT port of the first PXIe-5551 module to the REF IN port of the subsequent PXIe-5551 modules.