DAQCM_Export_Clk_On_Line Enumeration
- Updated2023-02-21
- 3 minute(s) read
Specifies the line that receives the pulse from the sample clock.
Namespace:
NationalInstruments.VeriStand.SystemDefinitionAPIAssembly: NationalInstruments.VeriStand.SystemDefinitionAPI (in NationalInstruments.VeriStand.SystemDefinitionAPI.dll) Version: 2013.0.0.0 (2013.0.0.0)
| Member name | Description |
|---|---|
| Default_RTSI_PXI_TRIG_0 | The RTSI 0 or PXI Trigger 0 line. This is the default setting. |
| PFI_0 | The PFI 0 line. |
| PFI_1 | The PFI 1 line. |
| PFI_10 | The PFI 10 line. |
| PFI_11 | The PFI 11 line. |
| PFI_12 | The PFI 12 line. |
| PFI_13 | The PFI 13 line. |
| PFI_14 | The PFI 14 line. |
| PFI_15 | The PFI 15 line. |
| PFI_2 | The PFI 2 line. |
| PFI_3 | The PFI 3 line. |
| PFI_4 | The PFI 4 line. |
| PFI_5 | The PFI 5 line. |
| PFI_6 | The PFI 6 line. |
| PFI_7 | The PFI 7 line. |
| PFI_8 | The PFI 8 line. |
| PFI_9 | The PFI 9 line. |
| RTSI_PXI_TRIG_0 | The RTSI 0 or PXI Trigger 0 line. |
| RTSI_PXI_TRIG_1 | The RTSI 1 or PXI Trigger 1 line. |
| RTSI_PXI_TRIG_2 | The RTSI 2 or PXI Trigger 2 line. |
| RTSI_PXI_TRIG_3 | The RTSI 3 or PXI Trigger 3 line. |
| RTSI_PXI_TRIG_4 | The RTSI 4 or PXI Trigger 4 line. |
| RTSI_PXI_TRIG_5 | The RTSI 5 or PXI Trigger 5 line. |
| RTSI_PXI_TRIG_6 | The RTSI 6 or PXI Trigger 6 line. |
| RTSI_PXI_TRIG_7 | The RTSI 7 or PXI Trigger 7 line. |
Remarks
 Note: |
|---|
The PXI trigger bus is the timing bus that connects PXI DAQ devices directly. The RTSI bus is the timing bus that connects PCI DAQ devices directly. These buses are functionally equivalent. |