USRP-2953 40 MHz Block Diagram
- Updated2023-02-20
- 3 minute(s) read
USRP-2953 40 MHz Block Diagram
Signals received by the USRP-295340 MHz are amplified, downconverted, filtered, digitized, and decimated before being passed to the host computer. Signals transmitted by the USRP-295340 MHz are upsampled, reconstructed, filtered, upconverted, and amplified before being transmitted.
The following lists describe the individual blocks:
Receive Path:
- The low-noise amplifier and drive amplifier amplify the incoming signal.
- The phase-locked loop (PLL) controls the voltage-controlled oscillator (VCO) so that the device clocks and local oscillator (LO) can be frequency-locked to a reference signal.
- The mixer downconverts the signals to the baseband in-phase (I) and quadrature (Q) components.
- The lowpass filter reduces noise and high frequency components in the signal.
- The analog-to-digital converter (ADC) digitizes the I and Q data.
- The digital downconverter (DDC) mixes, filters, and decimates the signal to a user-specified rate.
- The downconverted samples are passed to the host computer over a standard gigabit Ethernet connection.
Transmit Path:
- The host computer synthesizes baseband I/Q signals and transmits the signals to the device over a standard gigabit Ethernet connection.
- The digital upconverter (DUC) mixes, filters, and interpolates the signal to 400 MS/s.
- The digital-to-analog converter (DAC) converts the signal to analog.
- The lowpass filter reduces noise and high frequency components in the signal.
- The mixer upconverts the signals to a user-specified RF frequency.
- The PLL controls the VCO so that the device clocks and LO can be frequency-locked to a reference signal.
- The transmit amplifier amplifies the signal and transmits the signal through the antenna.
USRP-2953 120 MHz Block Diagram
Signals received by the USRP-2953120 MHz are amplified, downconverted, filtered, digitized, and decimated before being passed to the host computer. Signals transmitted by the USRP-2953120 MHz are upsampled, reconstructed, filtered, upconverted, and amplified before being transmitted.
The following lists describe the individual blocks:
Receive Path:
- The low-noise amplifier and drive amplifier amplify the incoming signal.
- The phase-locked loop (PLL) controls the voltage-controlled oscillator (VCO) so that the device clocks and local oscillator (LO) can be frequency-locked to a reference signal.
- The mixer downconverts the signals to the baseband in-phase (I) and quadrature (Q) components.
- The lowpass filter reduces noise and high frequency components in the signal.
- The analog-to-digital converter (ADC) digitizes the I and Q data.
- The digital downconverter (DDC) mixes, filters, and decimates the signal to a user-specified rate.
- The downconverted samples are passed to the host computer over a standard gigabit Ethernet connection.
Transmit Path:
- The host computer synthesizes baseband I/Q signals and transmits the signals to the device over a standard gigabit Ethernet connection.
- The digital upconverter (DUC) mixes, filters, and interpolates the signal to 400 MS/s.
- The digital-to-analog converter (DAC) converts the signal to analog.
- The lowpass filter reduces noise and high frequency components in the signal.
- The mixer upconverts the signals to a user-specified RF frequency.
- The PLL controls the VCO so that the device clocks and LO can be frequency-locked to a reference signal.
- The transmit amplifier amplifies the signal and transmits the signal through the antenna.