USB-6509 Digital Filtering

Use the digital filter option available on the USB-6509 input lines to eliminate glitches on input data. You can use the digital filtering with change detection to reduce the number of changes to examine and process.

You can configure the digital input channels to pass through a digital filter, and control the timing interval the filter uses. The filter blocks pulses that are shorter than half of the specified timing interval and passes pulses that are longer than the specified interval. Intermediate-length pulses—pulses longer than half of the interval but less than the interval—may or may not pass the filter.

The following table lists the pulse widths guaranteed to be passed and blocked.

Table 6. USB-6509 Digital Filtering
Filter Setting Pulse Width Guaranteed to Pass Filter Pulse Width Guaranteed to Not Pass Filter
400 ns ≤ tinterval ≤ 209.7152 ms tinterval tinterval /2

You can enable digital filtering on as many input lines as necessary for your application. All filtered lines share the same timing interval, which ranges from 400 ns to 209.7152 ms.

Internally, the filter uses the sample clock and the filter clock.

  • Sample Clock—The sample clock has a frequency of 48 MHz that corresponds to a period of 20.83 ns. The input signal is sampled on each rising edge of the sample clock. However, a change in the input signal is recognized only if it maintains its new state for at least two consecutive rising edges of the filter clock.
  • Filter Clock—The filter clock is generated by a counter and has a period equal to one half of the specified timing interval. The filter clock is programmable and allows you to control how long a pulse must last to be recognized. The sample clock provides a fast sample rate to ensure that input pulses remain constant between filter clocks.

    • Digital Filtering Example

    The following figure shows a filter configuration with a 208 ns filter interval (104 ns filter clock).

    Figure 8. Digital Filtering Example

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    • Periods A and B: The filter blocks the glitches because the external signal does not remain steadily high from one rising edge of the filter clock to the next.
    • Period C: The filter passes the transition, because the external signal remains steadily high.

    Depending on when the transition occurs, the filter may require up to two filter clocks—one full filter interval—to pass a transition. The figure shows a rising (0 to 1) transition. The same filtering applies to falling (1 to 0) transitions.