The USB-6451 features four digital output (waveform generation) timing signals.

  • DO Sample Clock Signal
  • DO Sample Clock Timebase Signal
  • DO Start Trigger Signal
  • DO Pause Trigger Signal

DO Sample Clock Signal

The USB-6451 uses the DO Sample Clock (do/SampleClock) signal to update the DO terminals with the next sample from the DO waveform generation FIFO.

You can specify an internal or external source for DO Sample Clock. You can also specify whether the DAC update begins on the rising edge or falling edge of DO Sample Clock. If the USB-6451 receives a DO Sample Clock when the FIFO is empty, the USB-6451 reports an underflow error to the host software.

Using an Internal Source

One of the following internal signals can drive DO Sample Clock:

  • DI Sample Clock (di/SampleClock)
  • DO Sample Clock (do/SampleClock)
  • AI Sample Clock (ai/SampleClock)
  • AI Convert Clock (ai/ConvertClock)
  • AO Sample Clock (ao/SampleClock)
  • Counter n Sample Clock
  • Counter n Internal Output
  • Frequency Output
  • DI Change Detection output

Several other internal signals can be routed to DO Sample Clock through internal routes. Refer to Device Routing in MAX for more information.

Using an External Source

Use DIO <0..15> as the source of DO Sample Clock.

Routing DO Sample Clock to an Output Terminal

You can route DO Sample Clock (as an active low signal) out to any DIO <0..15> terminal.

Other Timing Requirements

The DO timing engine on the USB-6451 internally generates DO Sample Clock unless you select some external source. DO Start Trigger starts the timing engine and either the software or hardware can stop it once a finite generation completes. When using the DO timing engine, you can also specify a configurable delay from DO Start Trigger to the first DO Sample Clock pulse. By default, this delay is two ticks of DO Sample Clock Timebase. The following figure shows the relationship of DO Sample Clock to DO Start Trigger

Figure 50. DO Sample Clock and DO Start Trigger


DO Sample Clock Timebase Signal

The DO Sample Clock Timebase (do/SampleClockTimebase) signal is divided down to provide a source for DO Sample Clock.

You can route any of the following signals to be the DO Sample Clock Timebase signal:

  • 100 MHz Timebase (default)
  • 20 MHz Timebase
  • 100 kHz Timebase
  • DIO <0..15>

DO Sample Clock Timebase is not available as an output on the I/O connector.

You might use DO Sample Clock Timebase if you want to use an external sample clock signal, but need to divide the signal down. If you want to use an external sample clock signal, but do not need to divide the signal, then you should use DO Sample Clock rather than DO Sample Clock Timebase.

DO Start Trigger Signal

Use the DO Start Trigger (do/StartTrigger) signal to initiate a waveform generation. If you do not use triggers, you can begin a generation with a software command.

Retriggerable DI

The DO Start Trigger is configurable as retriggerable. When DO Start Trigger is configured as retriggerable, the timing engine generates the sample clocks for the configured generation in response to each pulse on a DO Start Trigger signal.

The timing engine ignores the DO Start Trigger signal while the clock generation is in progress. After the clock generation is finished, the timing engine waits for another start trigger to begin another clock generation. The following figure shows a retriggerable DO of four samples.

Figure 51. Retriggerable DO


Using a Digital Source

To use DO Start Trigger with a digital source, specify a source and an edge. The source can be any of the following signals:

  • A pulse initiated by host software
  • DIO <0..15>
  • AI Start Trigger (ai/StartTrigger)
  • AI Reference Trigger (ai/Reference Trigger)
  • AO Start Trigger (ao/StartTrigger)
  • Counter n Internal Output
  • DI Start Trigger (do/StartTrigger)
  • DI Reference Trigger (di/ReferenceTrigger)
  • Change Detection Event

The source can also be one of several other internal signals on the USB-6451. Refer to Device Routing in MAX for more information.

You can also specify whether the measurement acquisition begins on the rising edge or falling edge of DI Start Trigger.

Routing DO Start Trigger to an Output Terminal

You can route DO Start Trigger out to any DIO <0..15> terminal. The output is an active high pulse. All DIO terminals are configured as inputs by default.

DO Pause Trigger Signal

Use the DO Pause Trigger (do/PauseTrigger) signal to mask off samples in a DAQ sequence. That is, when DO Pause Trigger is active, no samples occur.

DO Pause Trigger does not stop a sample that is in progress. The pause does not take effect until the beginning of the next sample.

When you generate digital output signals, the generation pauses as soon as the pause trigger is asserted. If the source of your sample clock is the onboard clock, the generation resumes as soon as the pause trigger is deasserted, as shown in the following figure.

Figure 52. DO Pause Trigger with the Onboard Clock Source


If you are using any signal other than the onboard clock as the source of your sample clock, the generation resumes as soon as the pause trigger is deasserted and another edge of the sample clock is received, as shown in the following figure.

Figure 53. DO Pause Trigger with Other Signal Source


Using a Digital Source

To use DO Pause Trigger, specify a source and a polarity. The source can be one of the following signals:

  • DIO <0..15>
  • Counter n Internal Output
  • Counter n Gate
  • AI Pause Trigger (ai/PauseTrigger)
  • AO Pause Trigger (ao/PauseTrigger)
  • DI Pause Trigger (di/PauseTrigger)

The source can also be one of several other internal signals on the USB-6451. Refer to Device Routing in MAX for more information.

You can also specify whether the samples are paused when DO Pause Trigger is at a logic high or low level.

Routing DI Pause Trigger Signal to an Output Terminal

You can route DI Pause Trigger out to any DIO <0..15> terminal.