You can enable a programmable debouncing filter on each digital line on Port 0. These filters are available when you use the digital line for input.

When the filters are enabled, your device samples the input on each rising edge of a filter clock. The USB-6451 divides down the onboard 100 MHz or 100 kHz clocks to generate the filter clock. The following is an example of low-to-high transitions of the input signal. High-to-low transitions work similarly.

Assume that an input terminal has been low for a long time. The input terminal then changes from low-to-high, but glitches several times. When the filter clock has sampled the signal high on two consecutive edges, and the signal remained stable in between, the low-to-high transition is propagated to the rest of the circuit.

Table 21. Filters
Filter Setting Filter Clock Pulse Width Guaranteed to Pass Filter Pulse Width Guaranteed to Not Pass Filter
Short 12.5 MHz 160 ns 80 ns
Medium 195.3125 kHz 10.24 µs 5.12 µs
High 390.625 Hz 5.12 ms 2.56 ms
None — — —

The filter setting for each input can be configured independently. On power up, the filters are disabled. The following figure shows an example of a low-to-high transition on an input.

Figure 55. Input Low-to-High Transition


When multiple lines are configured with the same filter settings, they are considered a bus. There are two filtering modes for use with multiple lines: line filtering and bus filtering.

  • Line filtering—Each line transitions independently of the other lines in the bus and acts like the behavior described above.
  • Bus filtering—If any line in the bus has jitter, then all lines in the bus hold the state until the bus becomes stable.

    • Each individual line only waits 
one extra filter tick before changing, which prevents a noisy line from holding a valid transition indefinitely. With bus mode, if all the bus line transitions become stable in less than one filter clock period and the bus period is more than two filter clock periods, then all the bus lines are guaranteed to be correlated at the output of the filter.

    You can think of the behavior for each transition as a state machine. If a line transitions and stays high for two consecutive filter clock edges, then one of two options occurs:

    Case 1

    If no transitions have occurred on the other lines, the transition propagates on the second filtered clock edge, as shown in the following figure.

    Figure 56. Case 1


    Case 2

    If an additional line on the bus also has a transition during the filter clock period, the change is not propagated until the next filter clock edge, as shown in the following figure.

    Figure 57. Case 2


    The following figure illustrates the difference between line and bus filtering.

    Figure 58. Line and Bus Filtering


    2A With line filtering, filtered input A would ignore the glitch on digital input P0.B and transition after two filter clocks.
    3A Filtered input A goes high when sampled high for two consecutive filter clocks and transitions on the next filter edge because digital input P0.B glitches.