Counter Output Applications

You can specify a delay from when the counter is armed to the beginning of the pulse. The delay is measured in terms of a number of active edges of the Source input.

You can specify a pulse width. The pulse width is also measured in terms of a number of active edges of the Source input. You can also specify the active edge of the Source input (rising or falling).

The following figure shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of the pulse. You can also specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the Source input.

After the Start Trigger signal pulses once, the counter ignores the Gate input.

The following figure shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

With USB-6421 counters, the primary counter generates the specified pulse train and the embedded counter counts the pulses generated by the primary counter. When the embedded counter reaches the specified tick count, it generates a trigger that stops the primary counter generation. The following figure shows an example of finite pulse train generation.

In Legacy Mode, the counter operation requires two counters and does not use the embedded counter. For example, to generate four pulses on Counter 0, Counter 0 generates the pulse train, which is gated by the paired second counter. The paired counter, Counter 1, generates a pulse of desired width.

The routing is done internally. The following figure shows an example finite pulse train timing diagram.

You can route the start trigger signal to the gate input of the counter. You can specify a delay from the start trigger to the beginning of each pulse. You can also specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the source input. You can apply the initial delay to only the first trigger or to all triggers using the CO.EnableInitalDelayOnRetrigger property. The default for a single pulse is true, while the default for finite pulse trains is false.

The counter ignores the gate input while a pulse generation is in progress. After the pulse generation is finished, the counter waits for another start trigger signal to begin another pulse generation. For retriggered pulse generation, pause triggers are not allowed since the pause trigger also uses the gate input.

The following figure shows a generation of two pulses with a pulse delay of five and a pulse width of three (using the rising edge of Source) with CO.EnableInitalDelayOnRetrigger set to the default true.

The following figure shows the same pulse train with CO.EnableInitalDelayOnRetrigger set to the default false.

The minimum time between the trigger and the first active edge is two ticks of the source.

You can specify a delay from when the counter is armed to the beginning of the pulse train. The delay is measured in terms of a number of active edges of the source input.

You specify the high and low pulse widths of the output signal. The pulse widths are also measured in terms of a number of active edges of the source input. You can also specify the active edge of the source input (rising or falling).

The counter can begin the pulse train generation as soon as the counter is armed or in response to a hardware start trigger. You can route the start trigger to the gate input of the counter.

You can also use the gate input of the counter as a pause trigger (if it is not used as a start trigger). The counter pauses pulse generation when the pause trigger is active. The following figure shows a continuous pulse train generation (using the rising edge of source).

Continuous pulse train generation is sometimes called frequency division. If the high and low pulse widths of the output signal are M and N periods, then the frequency of the Counter n Internal Output signal is equal to the frequency of the source input divided by M + N.

Each point you write generates a single pulse. The number of pairs of idle and active times (pulse specifications) you write determines the number of pulses that are generated. All points are generated back to back to create a user-defined pulse train.

The following table and figure detail a finite implicit generation of three samples.

When a sample clock occurs, the current pulse (idle followed by active) finishes generation and the next pulse updates with the next sample specifications.

The following table and figure detail a finite sample clocked generation of three samples where the pulse specifications from the create channel are two ticks idle, two ticks active, and three ticks initial delay.

The USB-6421 supports three methods of continuous generation for controlling what data is written: regeneration, FIFO regeneration, and non-regeneration.

Regeneration—Data that is already in the buffer repeats. Data from the PC buffer is continually downloaded to the FIFO to be written out. New data can be written to the PC buffer at any time without disrupting the output.

FIFO Regeneration—The entire buffer is downloaded to the FIFO and regenerated from the FIFO. Once the data is downloaded, new data cannot be written to the FIFO. To use FIFO regeneration, the entire buffer must fit within the FIFO size. The advantage of using FIFO regeneration is that it does not require communication with the main host memory once the operation starts, thereby preventing any problems that might occur due to excessive bus traffic.

Non-Regeneration—Old data is not repeated. New data must be continually written to the buffer. If the program does not write new data to the buffer at a fast enough rate to keep up with the generation, the buffer underflows and causes an error.