Disabling Synchronization Registers for Proper DRAM Function
- Updated2023-02-20
- 1 minute(s) read
Disabling Synchronization Registers for Proper DRAM Function
Note All NI PXI version 1.1 and later CLIP
items and all NI PXI Express CLIP items automatically disable all synchronization
registers.
- Right-click a DRAM interface signal and select Properties from the shortcut menu to open the FPGA I/O Properties dialog box.
- Select Advanced Code Generation in the Category list to open the Advanced Code Generation page.
- Select 0 in the Number of Synchronizing Registers for Output Data box to disable all synchronization registers for that signal. Always disable synchronization registers for synchronous interfaces when proper operation depends on no latency.