Prototyping Area

Most of the board consists of the prototyping areas, which are filled with hole arrays of 2.54 mm (0.100 in.) pitch. These are all plated holes to ease soldering. There are five main grid areas for prototyping: Bank 1, Bank 2, Bank 3, Bank 4, and RTI. Each bank gives access to signals of the corresponding bank on the CPLD as well as to the corresponding bank VCCO. Banks 1 and 2 also provide access to the front panel connectors.

The RTI grid contains holes connected to the rear I/O connectors, XJ02 and XJ03, along with several grounds, access to the 24 V supply from the backplane, and two pairs of holes connected to each of the bank rails.

Each of the five grids has its own coordinate system. Rows are numbered from top to bottom, and columns are marked with letters from left to right. Hole A1 is always at the top-left corner. These coordinates are referenced in this document.

For a detailed assignment of the hole arrays, refer to the SLSC-12101 pinout sections of this manual.