Logic Analyzer Connector

A 43-pin MICTOR Connector is placed between the CPLD and SLSC Interface connector for direct monitoring of the signals using a logic analyzer. In addition to the SLSC signals, 17 debug lines are connected directly from the CPLD to the connector. In the shipping CPLD image, two of these lines are controlled by DIO ports, one line is a copy of the internal 40 MHz clock, and 14 lines are only driven to GND. You can use all 17 lines to monitor internal signals of your design. See pinout sections for more information on the signal routing to this connector.