FPGA DIO
- Updated2023-10-23
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FPGA DIO
The RMC has 96 2.5 V/3.3 V single-ended I/O or 45 differential pairs. The NI sbRIO-96xx is tested with all DIO channels driving ±3 mA DC loads. FPGA DIO startup states are dependent on the FPGA_VIO power rails, which do not provide valid voltages until after the FPGA is configured. This allows the user to correctly configure the FPGA_VIO voltage levels and prevent accidental damage to connected circuitry.
To ensure startup values, prior to FPGA configuration, place pull-up or pull-down resistors on the RMC DIO channel. When placing pull-up resistors, NI recommends pulling up to FPGA_VIO. Receiving circuitry that interfaces with the RMC DIO should also be powered from FPGA_VIO to ensure stable startup states. The DIO channels on the NI sbRIO-96xx are routed with a 55 Ω characteristic trace impedance. Route all RMCs with a similar impedance to ensure the best signal quality.
Signals ending in a P or N route loosely differential. If you implement them as differential signals, route with 100 Ω differential impedance on your board. If you implement them as single-ended signals, break them into two seperate traces with 55 Ω impedance each.