The NI sbRIO device provides 3.3 V output, 5 V tolerant input digital I/O via the 50-pin IDC headers.
The following figure shows the circuitry of one 3.3 V DIO channel on the J4 or J5 IDC header.
Figure 23. Circuitry of One 3.3 V DIO Channel on the J4 or J5 IDC Header
The NI sbRIO device is tested with all DIO channels driving ±3 mA DC loads. DIO signals are tristated (floating) before and during FPGA configuration. After FPGA configuration completes, unused DIO signals remain tristated. Refer to
3.3 V Digital I/O on 50-Pin IDC Connector section in the NI sbRIO-9637 Specifications on ni.com/manuals for the logic levels.
