Power Rails Signal Definitions

The following table describes the power rails pins and signals on the sbRIO device connector.
Table 5. Power Rails Signal Definitions
Signal Name Dedicated Pin # Direction (from Host System) I/O Standard Description
3.3V_AUX 48 O — 3.3 V_AUX from the RMC connector host system. The rail is always on when the main host system is connected to power.
FPGA_VIO

234

240

O — I/O voltage for the FPGA 3.3 V pins.
5V

54

60

66

72

O — 5 V from the RMC connector host system.
5V C Series

86

91

O 5 V Signal-conditioned C Series DIO.
VIN_Filtered

1

7

14

20

I — 9 V to 30 V input to power the sbRIO device through the RMC connector rather than through the front panel connector.