Introduction to TD-SCDMA (3GPP TDD-LCR)

3GPP TDD(Time domain duplexed) is a standard defined by the Third Generation Partnership Project. 3GPP TDD-LCR is a low chip rate (LCR) variant of the 3GPP TDD standard. More information on the 3GPP TDD-LCR standard can be found in the following 3GPP specifications:

The chip rate used by 3GPP TDD-LCR is 1.28 Mchips per second. The frame length is 10 ms, with each frame being made up of two 5 ms (6400 chip) sub-frames. The layout of the sub-frame can be seen in the following figure.

Fig. 6-1 TDD-LCR sub-frame

The TDD-LCR sub-frame consists of 7 traffic time slots, a DwPts (Downlink pilot time slot), a guard period and a UpPts (Uplink pilot time slot). The first traffic time slot transmitted (Ts0) must carry downlink data. The second time slot transmitted must carry uplink data. The data carried in Ts2 to Ts6 is determined by the position of the switching point: the timeslots before the switching point carry uplink data and the timeslots after the switching point carry downlink data.

DwPts (Downlink Pilot Time Slot)

The DwPts consists of a 32-chip guard period (GP) followed by a 64-chip synchronization code (SYNC-DL). The layout of the DwPts can be seen in the following figure.

Fig. 6-2 DwPts

During the guard period nothing is transmitted. The SYNC-DL consists of a 64-chip complex sequence. The complex sequence is generated from one of the 32 basic SYNC-DL sequences defined in Annex AA.1 of TS 25.223. The basic SYNC-DL code is converted to bipolar to form a bipolar sequence S. The bipolar sequence S is then converted to a complex sequence S:

S_i

UpPts (Uplink Pilot Time Slot)

The UpPts consists of a 128-chip SYNC-UL code followed by a 32-chip guard period. The layout of the UpPts can be seen in the following figure.

Fig. 6-3 UpPts

The SYNC-UL consists of a 128 chip complex sequence. The complex sequence is generated from one of the 256 basic SYNC-UL sequences defined in Annex AA.2 of TS 25.223. The basic SYNC-UL code is converted to bipolar form to form the bipolar sequence S. The bipolar sequence S is then converted to a complex sequence S:

S_i=(j)ⁱ.S_i where S_i ε{1,-1}, i=1,...,128, j=√ -1  Basic SYNC-UL sequence S to complex sequence S

Traffic Time Slots

The traffic slots are 864 chips long. Each traffic slot consists of a number of channels which are summed together to form the traffic slot’s chips. The layout of a channel is shown in the following figure.

Fig. 6-4 Burst layout

The data sent in a data burst is QPSK, 8PSK, or QAM modulated, multiplied by a channel-specific multiplier, spread by an orthogonal Walsh code and scrambled as shown in the following figure.

Fig. 6-5 Traffic channel structure

The following figure shows how the channels are combined to form the chips transmitted in each slot. RFmx Waveform Creator currently supports only QPSK or 8PSK modulation.

Fig. 6-6 Combining channel data to form slot data

Channel Weighting

The channel specific multiplier is dependent on both the channel code k and the spreading factor Q. The following figure shows the channel specific multipliers used in 3GPP TDD-LCR.

Table 6-1 Channel-specific multipliers

Channel Spreading

The data in each of the traffic channels is spread by a spreading code of W_Q^(k) where k is the channel code and q is the spreading factor. Channels in the same time slot can use different spreading factors (values of Q) providing the spreading code is orthogonal to the other channel codes used in the timeslot. The following figure shows the spreading tree for spreading factors 1 to 4. A channel code will be orthogonal if the specific code is not in use, no other code on the path from the specific code to the root of the tree is used, and no other code in the sub-tree below the specific code is used.

Fig. 6-7 Code-tree for 3GPP TDD-LCR channelization

Scrambling

The complex scramble code V is 16 chips long and is generated from one of the 128 bipolar sequences defined in Annex A of TS 25.223. The bipolar scramble code V is converted to a complex scrambling code as shown below:

V_i=(j)ⁱ.V_i where S_i ε{1,-1}, i=1,...,16, j=√ -1  Bipolar scramble sequence V to complex scramble sequence V

When scrambling, the data is taken Q_MAX/Q_k spread words at a time where Q_MAX = 16 (the maximum spreading factor), and Q_k = The spreading factor used by the channel. This means the data is taken in 16-chip blocks. Each chip in each 16 chip block is multiplied by the corresponding chip in the scramble code to produce scrambled data.

Slot Formats

A Traffic channel’s data burst can be used to transmit Traffic data, TFCI (Transport Format Combination Indicator) bits, SS (Synchronization Shift) bits and TPC (Transmitter Power Control) bits. A channel’s slot format determines which spreading factor the channel should use and how many Traffic data, TFCI, SS, and TPC bits are transmitted in the channel’s data bursts. The QPSK downlink slot formats are defined in Table 8F of TS 25.221. QPSK uplink slot formats are defined in Table 8G of TS 25.221 and 8PSK(uplink and downlink) slot formats are defined in Table 8H of TS 25.221. The following figure shows the positions of the TFCI, SS, and TPC bits in the channel’s data bursts.

Fig. 6-8 Location of the TFCI, SS, and TPC bits

TFCI-bits

The TFCI is encoded to form a TFCI code word. The TFCI codeword is modulated and spread in the same was as the other data being transmitted. The TFCI codeword is transmitted over one frame (two sub-frames). Normally, the TFCI codeword is split into four parts and transmitted as shown in the following figure.

Fig. 6-9 TFCI code word location (when TFCI code word requires four or more chips)

When the TFCI code requires fewer than four symbols (before spreading) to transmit, the codeword is split into only two parts and the TFCI is transmitted as shown in the following figure (only transmitting in the first data burst of each sub-frame).

Fig. 6-10 TFCI code word location (when TFCI code word requires fewer than four chips)

The length of the TFCI code word is determined by the slot format. The type of coding used to encode the TFCI is dependent on the TFCI code word length and modulation type. The following table shows the TFCI coding used in 3GPP TDD-LCR.

Table 6-2 TFCI coding

SS-bits

The SS (Synchronization Shift) bits are used to transmit uplink synchronization control. The SS bits are used to command a timing adjustment of (k/8) Tc every M sub-frames, where the values of k and M are signalled by the network and Tc is the chip period. The relationships between bits and synchronization Shifts are shown in the following figures (for QPSK and 8 PSK respectively).

Table 6-3 Coding of the SS for QPSK

Table 6-4 Coding of the SS for 8PSK

TPC-bits

The TPC (Transmitter Power Control) bits are used to increase/decrease the channel power. The relationships between bits and power control commands are shown in the following figures (for QPSK and 8 PSK respectively).

Table 6-5 TPC Bits for QPSK

Table 6-6 TPC Bits for 8PSK

Midamble Generation

The midamble sequence is determined by the basic midamble code in use, the maximum number of users, and the user id of the channel. The midamble sequence is generated from one of the 128 basic midamble codes defined in defined in Annex AA.1 of TS 25.221. The midamble code is first converted to a bipolar to form a bipolar sequence (M). The bipolar sequence is converted to a complex midamble sequence as described in the following figure.

Fig. 6-11 Midamble generation

Code Groups

The SYNC-DL codes, SYNC-UL codes, scrambling codes, and basic midamble codes are grouped into 32 groups. Each code group contains one SYNC-DL code, 8 SYNC-UL codes, and 4 basic midamble and scrambling codes. The following table shows the codes associated with each code group. The 3GPP TDD-LCR spec states that only codes from the same group can be used at any given time, and that the midamble code ID and scrambling code ID must be the same.

Table 6-7 3GPP TDD-LCR code grouping