Downlink Configuration

This tab allows you to configure the downlink signal. It comprises of two tabs - Downlink Configuration and Downlink Channels.

Downlink Configuration is for overall configuration of the downlink signal and Downlink Channel Configuration is for modifying the transmitted downlink channels.

The following changes are needed in the Downlink Channel Configuration tab.

HS-PDSCH Mode

The HS-PDSCH mode of operation can be set to either SISIO/Diversity or MIMO. Default value is SISO/Diversity.

The Precoding Pattern, the Slot Format 2, and the Stream 2 Data Source parameters are visible only when HS-PDSCH Mode is MIMO and Select Channel Type is HS-PDSCH.

For the downlink, the spreading and scrambling operation is the same for all channels except for the synchronization channel (SCH). The process is shown in the following figure. The modulation scheme is QPSK for all channels except SCH, which consists of a sequence of real-valued symbols and the HS-DSCH. The HS-DSCH uses both QPSK, 16 QAM, and 64 QAM. The symbols can take the values + 1, - 1, and 0, where 0 indicates DTX.

For channels using QPSK, each pair of two consecutive symbols is mapped to an I and a Q branch in a serial to parallel manner. The modulation mapper is such that even- and odd-numbered symbols are mapped to the I and Q branch respectively. The I and Q branches are then spread to the chip rate using a channelization code C_ch,SF,m. The real-valued sequences on the I and Q branches are then treated as complex pairs and scrambled with a complex code S_dl,n.

For physical channels using 16QAM or 64 QAM, a set of consecutive symbols is serial-to-parallel converted and then mapped to 16QAM or 64QAM by a modulation mapper. The I and Q branches are both spread to the chip rate by the same real-valued channelization code C_ch,16,m. The sequences of real-valued chips on the I and Q branch are treated as a single complex-valued sequence of chips. This sequence of chips from all multi-codes is summed and scrambled by a complex-valued scrambling code S_dl,n.

Spreading and scrambling for all downlink channels except for SCH is as shown in the following figure.

The different downlink channels are combined as shown in the following figure.

Channelization Codes

The channelization codes are same as the OVSF codes used in the uplink. The channelization code for the primary CPICH is fixed to C_ch,256,0 and the channelization code for the primary CCPCH is fixed to C_ch,256,1. You control the channelization codes for all other channels.

Scrambling Code

A total of 2¹⁸-1 = 262143 scrambling codes, numbered from 0 to 262142, can be generated. However, only a subset of this number is used. The scrambling codes are divided into 512 sets, each containing a primary code and 15 secondary codes. The primary codes consist of codes n = 16i, where i = 0, 1 … 511. The set of secondary scrambling codes for the i^th set is defined as 16i + k, where k = 1, 2 ... 15.

The set of primary codes is further divided into 64 scrambling code groups, each consisting of eight primary scrambling codes. The j^th scrambling code group consists of primary scrambling codes 16 * 8 * j + 16k, where j = 0, 1 … 63 and k = 0, 1 … 7.

From the above, if we are given the primary code, we can obtain the secondary code by requesting a value 1, 2 … 15, We can also obtain the primary scrambling code group as [n/128]; where [] refers to the integer part and n is the code number.

The scrambling code sequences are constructed by combining two real sequences into a complex sequence. Each of the two real sequences is constructed as the position-wise modulo 2 sum of 38400 chip segments of two binary m-sequences generated by means of two generator polynomials of degree 18. The resulting sequences thus constitute segments of a set of Gold sequences. The scrambling codes are repeated for every 10 ms radio frame.

The following figure shows the implementation of the scrambling code.

Synchronization Codes

The synchronization codes are generated only for the first 256 chips of each slot. The primary SCH is same for each slot which is same for every cell in the system. However, this is not the same for secondary SCH. The secondary SCH consists of repeatedly transmitting a length 15 sequence of modulated codes of length 256 chips. The secondary synchronous code is denoted as c_s^i,k in the following figure where i = 0, 1 … 63 is the number of the primary scrambling code group, and k = 0, 1 … 14 is the slot number.

The actual code generated in each slot is obtained from the following table, that associates slot number, primary code group. Code number is used to generate the SCH channel.

Channel Structures

This section details the structure of each downlink channel.

Dedicated Downlink Physical Channel (DPCH)

The dedicated transport channel (DCH) is transmitted in time-multiplex with control information. The channel can be considered as time-multiplex of a downlink DPDCH and a downlink DPCCH. The following figure shows the frame structure of the downlink DPCH.

The number of bits in each field is dependent upon the slot format. More details are given in the following table.

*If TFCI bits are not used, then DTX is used in the TFCI field

The TFCI bits are calculated from a TFCI index. The pilot bit patterns for downlink DPCCH are given for information in the following table.

If compressed mode is used, Waveform creator takes the user-supplied slot format, compares this with other compressed mode parameters set by the user, and automatically applies the slot format as specified in the 3GPP FDD standards.

The relationship between power control and TPC bits is given in the following table.

Multicode transmission may be employed in the downlink. In other words, when multiple DPCHs are sent to one mobile. In such cases, control information is transmitted only on the first downlink DPCH and DTX bits are transmitted during the corresponding time period for the additional downlink DPCHs as depicted in the following figure.

E-DCH Relative Grant Channel (E-RGCH)

The E-RGCH is a fixed rate (30 kbps, SF = 128) dedicated downlink physical channel carrying the uplink E-DCH relative grants. The following figure illustrates the structure of the E-RGCH. A relative grant is transmitted using 3, 12, or 15 consecutive slots and in each slot a sequence of 40 ternary values is transmitted.

E-DCH Hybrid ARQ Indicator Channel (E-HICH)

The E-HICH is a fixed rate (30 kbps, SF = 128) dedicated downlink physical channel carrying the uplink E-DCH hybrid ARQ acknowledgement indicator. The preceding figure illustrates the structure of the E-HICH. A hybrid ARQ acknowledgement indicator is transmitted using 3 or 12 consecutive slots and in each slot a sequence of 40 ternary values is transmitted.

Fractional Dedicated Physical Channel (F-DPCH)

The F-PDCH is a fixed rate (3 kbps, SF = 256) downlink physical channel that carries 2 TPC bits per slot. The slot format is depicted in the following figure.

In each slot, the location of the TPC bits is given by the slot format for F-DPCH as detailed in the following figure.

Common Pilot Channel (CPICH)

The CPICH is a fixed rate (30 kbps, SF = 256) downlink physical channel that carries a predefined bit/symbol sequence 1 + j. There are primary CPICH and secondary CPICH(s). There can be only one primary CPICH per cell. It is scrambled with the primary scrambling code and is spread with C_ch,0,256. The secondary CPICH may be scrambled by either the primary or secondary scrambling code, there may be more than one per cell and an arbitrary channelization code with an SF of 256 can be used.

Primary Common Control Physical Channel (P-CCPCH)

The primary CCPCH is a fixed rate (30 kbps, SF = 256) downlink channel used to carry the BCH transport channel. The frame structure of this channel is shown in the following figure.

Secondary Common Control Physical Channel (S-CCPCH)

The structure of the S-CCPCH is shown in the following figure. The set of possible rates is the same as for the DPCH.

The number of bits associated with each field depends on the slot format. The slot format is automatically determined by.

Physical Downlink Shared Channel (PDSCH)

The frame and slot structure of the PDSCH is shown in the following figure.

The allowed data rates for the PDSCH are 15 to 960 ksps (SF = 256-4).

Paging Indicator Channel (PICH)

The Paging Indicator Channel is a fixed rate (SF= 256) physical channel that is used to carry the paging indicators. The structure of the paging channel is shown in the following figure. In this figure, it is important to note that the last 12 bits of the frame are not transmitted. The first 288 bits are used for paging indication. In each frame N_p indicators are sent where N_p = 18, 36, 72, 144.

Fig. 2-27 Structure of the PICH

The paging indicators can be represented as patterns of zeros and ones, {P₀, …P_q, …, P_Np-1}. converts the paging indicators to bits according to the 3GPP FDD standard.

High Speed Shared Control Channel (HS-SCCH)

The HS-SCCH is a fixed rate (60 kbps, SF=128) downlink physical channel used to carry downlink signaling related to High Speed Downlink Shared Channel (HS-DSCH) transmission. The frame and slot structure of the HS-SCCH is shown in the following figure.

High Speed Physical Downlink Shared Channel (HS-PDSCH)

The High Speed Physical Downlink Shared Channel (HS- PDSCH) is used to carry the High Speed Downlink Shared Channel (HS-DSCH).

A HS-PDSCH corresponds to one channelization code of fixed spreading factor SF=16 from the set of channelization codes reserved for HS-DSCH transmission. The HS-PDSCH does not carry any Layer 1 information; this is transmitted in the associated HS-SCCH.

The subframe and slot structure of the HS-PDSCH is shown in the following figure.

An HS-PDSCH may use QPSK or 16QAM modulation symbols. In the above figure, M is the number of bits per modulation symbol; i.e. M=2 for QPSK and M=4 for 16QAM. and M=6 for 64QAM The slot formats are shown in the following table.

E-DCH Absolute Grant Channel (E-AGCH)

The E-AGCH is a fixed rate (15 kbps, SF = 256) downlink physical channel carrying the uplink E-DCH absolute grant. The following figure illustrates the E-AGCH structure.

Channel Timing Offset

To reduce the crest factor, some channels are offset in time with respect to others. The offset is given as number of 256 chips. All the channels are phase-referenced to the primary common control channel. That is the channels that are offset in time should delay the multiplexed data by the equivalent of n*256 chips before spreading and scrambling. The allowed range is 0 to 149. For the E-AGCH, there is a constant frame timing offset of 20 which is relative to the P-CCPCH frame timing.

Configuring the Downlink

This section lists the parameters and methods provided by to define a 3GPP FDD downlink.

Scrambling Code: To set the scrambling code, enter the required code value in the edit box. Valid values are 0 to 8191.

Scrambling Code Group: Waveform Creator automatically calculates the scrambling code group depending on Scrambling Code. You can edit this value to override the automatic selection.

Control to Data Gain: You can set the relative power level in dB between the data and control parts of a channel. The allowed range is 0 to -60 dB.

Number of PI Per FrameYou can set the number of paging indicators per frame by choosing a value from the Number of PI per Frame combo box. Available values are: 18, 36, 72, and 144.

Number of Antennas: Specifies the number of antennas. Valid values are 1 and 2. The number of output files is equal to this number of antennas.

Transmit Diversity for Non-HS Channels: This checkbox can be modified only if the Number of Antennas greater than 1. If selected, transmit diversity will be applied on all channels other than the high-speed channels (HS-SCCH and HS-PDSCH). HS-SCCH diversity is controlled by its own parameter. HS-PDSCH diversity is applied if its mode is SISO/Tx Diversity and the number of antennas is greater than 1.

The second output file may contain no data if Transmit Diversity for non-HS channels is not enabled and if HS-PDSCH and CPICH are not configured and (a) HS-SCCH is not configured or (b) if HS-SCCH Tx Diversity is not selected when HS-SCCH is configured.

Enabling Synchronization Channels: To use synchronization channels select the Use SCHs check box. This lets you enter the relative powers of primary and secondary channels. Valid values are between 0 and -60 dB.

TFCI Bits: If you wish to generate TFCI bits, select the Use TFCI Bits box.

Compressed Mode: Enables compressed mode. To configure compressed mode, press the Configure button. This presents you with the dialog box as shown in the following figure.

It is possible to select three compressed mode methods and the frame structure. The parameters within the block diagram should be filled in with reference to compressed mode.

Editing, Adding, and Removing Downlink Channels

You can add, delete, and edit channels to the downlink simulation. Waveform Creator provides a table to define the channels. The table always shows the primary and the secondary common pilot channels (P-CPICH, S-CPICH), the primary and the secondary common control channels (P-CCPCH, S-CCPCH), the PICH, the PDSCH, the E-AGCH, the E-RGCH, and the E-HICH.

The following parameters can be altered:

• Power levels for all channels — Valid values are –60 to dB.
• Timing offset — Valid values are 0 to 149. The timing offset for P-CPICH, S-CPICH, P-CCPCH, PDSCH, and E-AGCH are constant and cannot be changed. For the first four channels, the timing offset is set to 0, while for the latter channel it is set to 20.
• For the number of slots for E-RGCH and E-HICH, you are presented with a combo box. Select the number of slots required. The allowed numbers of slots are 3, 12, and 15. The latter is only applicable to E-RGCH and EAGHC.
• The Sequence Index for E-RGCH and E-HICH. The valid range is 0 to 39.
• The relative grant (R.G.) and ARQ acknowledgment indicator (ARQ A.I.) for the E_RGCH and E-HICH, respectively. Valid values are +1 and –1. The 0 selection is not supported as for a 10 ms frame this results in a frame(s) with no data. A 0 selection is equivalent to switching the channel off.
• The data source can be changed for the P-CCPCH, S-CCPCH, PICH, and E-AGCH. This will show the standard data source dialog that will allow you to modify the current data source configuration.
• The channel state can be set to on or off for all channels.

In some situations, it is possible to configure two channels such that the channel code and spreading factor (determined by the current slot format) can overlap, leading to a conflict. When such a conflict occurs, an error graphic is shown indicating that the channels are in conflict, and each overlapping channel will be highlighted in red in the channel table as shown in the following figure.

Adding a Channel

To add a channel into your downlink simulation click Add button. The default channel is a dedicated physical channel. Select the slot format by clicking on the appropriate row. Enter each parameter as required. If the channel is a multicode channel, select the Multicode Channel check box. If this is selected you cannot define TPC bits. When the Add Channel Properties dialog box is open, the main downlink table will show the configured channel, allowing you to view any conflicts that occur as part of the channel configuration. Upon clicking OK, the current selection is accepted, and the channel will be permanently added to the table. Upon clicking Cancel, the channel will be automatically removed from the table.

In addition to the DPCH channel, you can also add an HS-SCCH channel, an HS-PDSCH channel, an OCNS and an F-DPCH channel. The OCNS channel is an orthogonal noise source. Furthermore, you can set the power level and channel code for all channel types. The slot format is used to set the symbol rate for all the available channels. No control bits are present in the HS-SCCH, HS-PDSCH, and OCNS channels.

HS-PDSCH-specific Parameters

For HS-PDSCH, refer the following figure, the following additional items are configurable.

Slot Format: Valid values are 0, 1, or 2, which corresponds to the modulation schemes, QPSK, 16QAM, and 64QAM respectively.

Slot Format 2: This is visible only if the HS-PDSCH mode is selected as “MIMO”. It is the slot format for the second transport block and reuses the values in the slot format table for the first transport block. Thus, it can take the values 0, 1 and 2. The second transport block’s modulation scheme can be configured independent of the first transport block’s.

Tx Pattern: This controls the subframes in which HS-PDSCH and the corresponding HS-SCCH are transmitted. It is a sequence of 1s and 0s, where 1 represents transmission and 0, no transmission. Default value is 1. The transmission pattern is applied each subframe, while wrapping around at the end of the pattern, to the HS-PDSCH assuming an offset of 2 slots from the start of the P-CCPCH frame.

Precoding Pattern: When MIMO mode is selected in HS-PDSCH Mode in the Downlink Channel Configuration, then the “Precoding pattern” box becomes visible. It corresponds to a pattern of precoding weights . It takes 0, 1, 2 and 3 as pattern values. Default is 0. The precoding weights are applied each subframe, while wrapping around at the end of the pattern, to the HS-PDSCH assuming an offset of 2 slots from the start of the P-CCPCH frame.

Stream 2 Data Source:This is visible only if the HS-PDSCH mode is selected as “MIMO”. It is the source of data for the second transport block.

F-DPCH Specific Parameters:For F-DPCH, most parameters are similar to the DPCH. The main difference is the replacement of Ndata1 and Ndata2 with NOFF1 and NOFF2 (refer the following figure).

Editing a Channel

To edit a channel, select the channel of interest and either double-click the right mouse button or press the Edit... button. On doing so, you are presented with a dialog box as shown in the following figure.

Edit the parameters of interest. Click OK when done. You cannot alter the type of channel.

Removing a Channel

To remove a channel, select the channel of interest and press the Remove button.