Scan is a technique for testing DUTs designed with internal test circuitry to validate that the digital logic in the DUT was properly manufactured. You can create scan patterns to test DUT circuitry using scan chains. Scan patterns contain scan pins (DUT pins in scan_in or scan_out mode) and scan vectors (which contain the scan opcode) but are otherwise the same as standard patterns. By serially shifting data into and out of the scan test pins, you can configure the DUT to test its functional circuitry. Dedicated scan features of the digital pattern instrument can help create patterns for scan testing.

To use the scan patterns, you can complete the following:

  • Create scan patterns as text or text pattern files (.digipatsrc) and then import the patterns into a Digital Pattern Editor project.
  • Create a regular pattern in the Digital Pattern Editor and then add scan pins and scan vectors to the pattern.

Scan Pins and Chains

You can select pattern pins for scan input or scan output. Scan input pins are restricted to pin states 0 and 1, and scan output pins are restricted to pin states L, H, and X. These restrictions apply only when you use these pins with a scan opcode. On non-scan vectors, these pins are regular DUT pins.

A scan chain is a pair of scan input pins and scan output pins.

Scan Vectors

Scan vectors are pattern vectors with the scan opcode. When the digital pattern instrument executes a scan vector, scan pins execute the scan pin data defined in the pattern. Non-scan pins repeats the pin state defined on the scan vector until the scan vector finishes.

You can call the Fetch History RAM Scan Cycle Numbers API to get the scan cycle numbers from the scan vector. Cycles that are not part of a scan vector return a -1 for the scan cycle numbers.

Scan vectors are compressed in vector memory. Using fewer scan chains per digital pattern instrument results in better vector memory compression. Splitting scan chains across digital pattern instruments can improve vector memory compression but could negatively impact performance of capture memory or History RAM when scan pins are used outside of scan vectors.

Scan Compression

Scan compression is triggered on scan vectors when the scan opcode is called. For scan vectors, only scan pins are allowed to change pins states. Scan compression provides a method for repurposing vector memory from non-scan pins, whose pin states are not changing each vector. This allows scan chains to grow longer than the maximum vector memory specification of the digital pattern instrument in certain use cases.

Scan compression is supported on up 16 scan chains. The level of compression that the pattern compiler can achieve depends on the number of scan chains defined in the pattern. The following table shows the estimated scan compression that is achievable based on the number of scan chains defined in the pattern. In use-cases where the number of scan in and scan out pins are not equal, use the greater of the two values. Scan compression is not possible when the number of scan in or scan out pins exceed 16.

Scan Chains Achievable Memory Compression Max Scan Chain
1 42x 5376M
2-3 21x 2688M
4-7 10x 1280M
8-11 5x 640M
12-15 3x 384M
16 2x 256M

Scan compression only applies to vectors associated with a scan opcode. Non-scan vectors are loaded into vector memory normally; therefore, this is not representative of the memory usage of the entire pattern set. However, with the proper pin distribution the scan opcode can significantly optimize memory usage of serial scan bitstreams.