The PXIe-5840 sets some hardware circuitry to certain states at power on and at device reset. The PXIe-5840 applies certain conditions to the device state upon FPGA reset.

Power On Conditions

Power on conditions are present after powering on or restarting the system and until an FPGA VI has been uploaded to the device.

  • DIO lines are configured as input terminals.
  • PFI 0 line is configured as an input terminal.
  • PXI trigger lines are not configured and appear to the bus as high impedance.
  • ADCs are configured by the board driver for 1.25 GS/s operation.
  • DACs are configured by the board driver 1.25 GS/s operation.

Reset Conditions

The following conditions apply to the FPGA reset device state, which is supported using the Reset Device button in MAX or by using the NI System Configuration API.

  • DIO lines are configured as input terminals.
  • PFI 0 line is configured as an input terminal.
  • PXI trigger lines are not configured and appear to the bus as high impedance; however, reservations are maintained.
  • ADC states are maintained.
  • DAC states are maintained.
Note Reset conditions apply only when using the instrument design libraries.

Download Conditions

The following conditions apply to the device state upon downloading a new FPGA VI to the PXIe-5840.

  • DIO lines are configured as input terminals.
  • PFI 0 line is configured as an input terminal.
  • PXI trigger lines are not configured and appear to the bus as high impedance; however, reservations are released.
  • ADC states are maintained.
  • DAC states are maintained.
Note The Data Clock is disabled immediately after downloading a new FPGA VI to the PXIe-5840. The driver re-enables the Data Clock automatically.